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| author | Andrew Jeffery | 2021-09-20 08:50:59 +0200 |
|---|---|---|
| committer | Cédric Le Goater | 2021-09-20 08:50:59 +0200 |
| commit | 709098fd37307a810ae4b8958ade348745b5c0fe (patch) | |
| tree | 1ba8dcb3fe606bce1cda6a9c7d9a225b11eba9d2 /include | |
| parent | hw: arm: aspeed: Enable mac0/1 instead of mac1/2 for g220a (diff) | |
| download | qemu-709098fd37307a810ae4b8958ade348745b5c0fe.tar.gz qemu-709098fd37307a810ae4b8958ade348745b5c0fe.tar.xz qemu-709098fd37307a810ae4b8958ade348745b5c0fe.zip | |
watchdog: aspeed: Sanitize control register values
While some of the critical fields remain the same, there is variation in
the definition of the control register across the SoC generations.
Reserved regions are adjusted, while in other cases the mutability or
behaviour of fields change.
Introduce a callback to sanitize the value on writes to ensure model
behaviour reflects the hardware.
Fixes: 854123bf8d4b ("wdt: Add Aspeed watchdog device model")
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20210709053107.1829304-2-andrew@aj.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/hw/watchdog/wdt_aspeed.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/hw/watchdog/wdt_aspeed.h b/include/hw/watchdog/wdt_aspeed.h index 80b03661e3..f945cd6c58 100644 --- a/include/hw/watchdog/wdt_aspeed.h +++ b/include/hw/watchdog/wdt_aspeed.h @@ -44,6 +44,7 @@ struct AspeedWDTClass { uint32_t reset_ctrl_reg; void (*reset_pulse)(AspeedWDTState *s, uint32_t property); void (*wdt_reload)(AspeedWDTState *s); + uint64_t (*sanitize_ctrl)(uint64_t data); }; #endif /* WDT_ASPEED_H */ |