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| author | Alistair Francis | 2019-06-18 03:31:08 +0200 |
|---|---|---|
| committer | Palmer Dabbelt | 2019-06-25 12:05:40 +0200 |
| commit | 747a43e818dc36bd50ef98c2b11a7c31ceb810fa (patch) | |
| tree | 13fea576f05a1532b2fdf82824a5791f36431b1c /include | |
| parent | target/riscv: Add the privledge spec version 1.11.0 (diff) | |
| download | qemu-747a43e818dc36bd50ef98c2b11a7c31ceb810fa.tar.gz qemu-747a43e818dc36bd50ef98c2b11a7c31ceb810fa.tar.xz qemu-747a43e818dc36bd50ef98c2b11a7c31ceb810fa.zip | |
target/riscv: Add the mcountinhibit CSR
1.11 defines mcountinhibit, which has the same numeric CSR value as
mucounteren from 1.09.1 but has different semantics. This patch enables
the CSR for 1.11-based targets, which is trivial to implement because
the counters in QEMU never tick (legal according to the spec).
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
[Palmer: Fix counter access semantics, change commit message to indicate
the behavior is fully emulated.]
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'include')
0 files changed, 0 insertions, 0 deletions