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| author | Daniel Henrique Barboza | 2021-12-17 17:57:18 +0100 |
|---|---|---|
| committer | Cédric Le Goater | 2021-12-17 17:57:18 +0100 |
| commit | 7aeac354a6925afcec684e985d56e612f9e81b2d (patch) | |
| tree | 77ed79d085d0a471f9f2ea1d9edad7814ef30ae2 /include | |
| parent | target/ppc: enable PMU instruction count (diff) | |
| download | qemu-7aeac354a6925afcec684e985d56e612f9e81b2d.tar.gz qemu-7aeac354a6925afcec684e985d56e612f9e81b2d.tar.xz qemu-7aeac354a6925afcec684e985d56e612f9e81b2d.zip | |
target/ppc/power8-pmu.c: add PM_RUN_INST_CMPL (0xFA) event
PM_RUN_INST_CMPL, instructions completed with the run latch set, is
the architected PowerISA v3.1 event defined with PMC4SEL = 0xFA.
Implement it by checking for the CTRL RUN bit before incrementing the
counter. To make this work properly we also need to force a new
translation block each time SPR_CTRL is written. A small tweak in
pmu_increment_insns() is then needed to only increment this event
if the thread has the run latch.
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211201151734.654994-8-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Diffstat (limited to 'include')
0 files changed, 0 insertions, 0 deletions