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| author | Peter Maydell | 2016-09-06 21:03:58 +0200 |
|---|---|---|
| committer | Peter Maydell | 2016-09-06 21:03:58 +0200 |
| commit | 7faae0b36e51ffdb17d4716ddc40dcfa682d93d9 (patch) | |
| tree | f08788b23327d24c3c1a400fc919e2d74e5c0dc8 /include | |
| parent | Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (diff) | |
| parent | block: m25p80: Fix vmstate structure name (diff) | |
| download | qemu-7faae0b36e51ffdb17d4716ddc40dcfa682d93d9.tar.gz qemu-7faae0b36e51ffdb17d4716ddc40dcfa682d93d9.tar.xz qemu-7faae0b36e51ffdb17d4716ddc40dcfa682d93d9.zip | |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20160906-1' into staging
target-arm queue:
* fix incorrect LPAE bit in FSR for alignment faults
* ACPI: fix the AML ID format for CPU devices to work for
large numbers of CPUs
* ast2400: add memory controller device model
* m25p80: fix the vmstate structure name (migration break)
# gpg: Signature made Tue 06 Sep 2016 20:02:28 BST
# gpg: using RSA key 0x3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg: aka "Peter Maydell <pmaydell@gmail.com>"
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20160906-1:
block: m25p80: Fix vmstate structure name
ARM: ACPI: fix the AML ID format for CPU devices
target-arm: Fix lpae bit in FSR on an alignment fault
ast2400: add a memory controller device model
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/hw/arm/ast2400.h | 2 | ||||
| -rw-r--r-- | include/hw/misc/aspeed_sdmc.h | 31 |
2 files changed, 33 insertions, 0 deletions
diff --git a/include/hw/arm/ast2400.h b/include/hw/arm/ast2400.h index 7833bc716c..e68807d475 100644 --- a/include/hw/arm/ast2400.h +++ b/include/hw/arm/ast2400.h @@ -15,6 +15,7 @@ #include "hw/arm/arm.h" #include "hw/intc/aspeed_vic.h" #include "hw/misc/aspeed_scu.h" +#include "hw/misc/aspeed_sdmc.h" #include "hw/timer/aspeed_timer.h" #include "hw/i2c/aspeed_i2c.h" #include "hw/ssi/aspeed_smc.h" @@ -32,6 +33,7 @@ typedef struct AST2400State { AspeedSCUState scu; AspeedSMCState smc; AspeedSMCState spi; + AspeedSDMCState sdmc; } AST2400State; #define TYPE_AST2400 "ast2400" diff --git a/include/hw/misc/aspeed_sdmc.h b/include/hw/misc/aspeed_sdmc.h new file mode 100644 index 0000000000..7e081f6d2b --- /dev/null +++ b/include/hw/misc/aspeed_sdmc.h @@ -0,0 +1,31 @@ +/* + * ASPEED SDRAM Memory Controller + * + * Copyright (C) 2016 IBM Corp. + * + * This code is licensed under the GPL version 2 or later. See the + * COPYING file in the top-level directory. + */ +#ifndef ASPEED_SDMC_H +#define ASPEED_SDMC_H + +#include "hw/sysbus.h" + +#define TYPE_ASPEED_SDMC "aspeed.sdmc" +#define ASPEED_SDMC(obj) OBJECT_CHECK(AspeedSDMCState, (obj), TYPE_ASPEED_SDMC) + +#define ASPEED_SDMC_NR_REGS (0x8 >> 2) + +typedef struct AspeedSDMCState { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + MemoryRegion iomem; + + uint32_t regs[ASPEED_SDMC_NR_REGS]; + uint32_t silicon_rev; + +} AspeedSDMCState; + +#endif /* ASPEED_SDMC_H */ |