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authorPeter Maydell2019-02-15 10:56:38 +0100
committerPeter Maydell2019-02-15 10:56:38 +0100
commit831a2fca343ebcd6651eab9102bd7a36b77da65d (patch)
treec73455bef9672616c6fa00313fba0ab47547ee60 /include
parenttarget/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR (diff)
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target/arm: Implement HACR_EL2
HACR_EL2 is a register with IMPDEF behaviour, which allows implementation specific trapping to EL2. Implement it as RAZ/WI, since QEMU's implementation has no extra traps. This also matches what h/w implementations like Cortex-A53 and A57 do. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190205181218.8995-1-peter.maydell@linaro.org
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