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| author | Peter Maydell | 2018-10-24 08:50:17 +0200 |
|---|---|---|
| committer | Peter Maydell | 2018-10-24 08:51:36 +0200 |
| commit | 8a0fc3a29fc2315325400c738f807d0d4ae0ab7f (patch) | |
| tree | 89df83c0a98a8b83bb0f994e6fcc0cd704d43004 /include | |
| parent | target/arm: ISR_EL1 bits track virtual interrupts if IMO/FMO set (diff) | |
| download | qemu-8a0fc3a29fc2315325400c738f807d0d4ae0ab7f.tar.gz qemu-8a0fc3a29fc2315325400c738f807d0d4ae0ab7f.tar.xz qemu-8a0fc3a29fc2315325400c738f807d0d4ae0ab7f.zip | |
target/arm: Implement HCR.VI and VF
The HCR_EL2 VI and VF bits are supposed to track whether there is
a pending virtual IRQ or virtual FIQ. For QEMU we store the
pending VIRQ/VFIQ status in cs->interrupt_request, so this means:
* if the register is read we must get these bit values from
cs->interrupt_request
* if the register is written then we must write the bit
values back into cs->interrupt_request
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20181012144235.19646-7-peter.maydell@linaro.org
Diffstat (limited to 'include')
0 files changed, 0 insertions, 0 deletions