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| author | Yongbok Kim | 2019-12-20 10:29:34 +0100 |
|---|---|---|
| committer | Aleksandar Markovic | 2020-01-29 19:28:52 +0100 |
| commit | 99029be1c2875cd857614397674bbf563ddb6f91 (patch) | |
| tree | 28c1dde351decde94f717efd13a1db2db8bd561d /include | |
| parent | target/mips: Amend CP0 WatchHi register implementation (diff) | |
| download | qemu-99029be1c2875cd857614397674bbf563ddb6f91.tar.gz qemu-99029be1c2875cd857614397674bbf563ddb6f91.tar.xz qemu-99029be1c2875cd857614397674bbf563ddb6f91.zip | |
target/mips: Add implementation of GINVT instruction
Implement emulation of GINVT instruction. As QEMU doesn't support
caches and virtualization, this implementation covers only one
instruction (GINVT - Global Invalidate TLB) among all TLB-related
MIPS instructions.
Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com>
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1579883929-1517-5-git-send-email-aleksandar.markovic@rt-rk.com>
Diffstat (limited to 'include')
0 files changed, 0 insertions, 0 deletions