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| author | BALATON Zoltan | 2018-03-26 01:54:28 +0200 |
|---|---|---|
| committer | David Gibson | 2018-04-27 10:05:22 +0200 |
| commit | 99d45f8fbd6756c2495bcb554dcbf50585f1f7b0 (patch) | |
| tree | f1f862efeda73aa98059ab4ffa2cf97843cf1c2c /include | |
| parent | ppc: Fix size of ppc64 xer register (diff) | |
| download | qemu-99d45f8fbd6756c2495bcb554dcbf50585f1f7b0.tar.gz qemu-99d45f8fbd6756c2495bcb554dcbf50585f1f7b0.tar.xz qemu-99d45f8fbd6756c2495bcb554dcbf50585f1f7b0.zip | |
target/ppc: Fix reserved bit mask of dstst instruction
According to the Vector/SIMD extension documentation bit 6 that is
currently masked is valid (listed as transient bit) but bits 7 and 8
should be reserved instead. Fix the mask to match this.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'include')
0 files changed, 0 insertions, 0 deletions