diff options
| author | Marc Zyngier | 2019-12-01 13:20:16 +0100 |
|---|---|---|
| committer | Peter Maydell | 2019-12-16 11:46:34 +0100 |
| commit | 9ca1d776cb49c09b09579d9edd0447542970c834 (patch) | |
| tree | 4c138b049175213a279178e8463f77d9469902cb /include | |
| parent | target/arm: Honor HCR_EL2.TID1 trapping requirements (diff) | |
| download | qemu-9ca1d776cb49c09b09579d9edd0447542970c834.tar.gz qemu-9ca1d776cb49c09b09579d9edd0447542970c834.tar.xz qemu-9ca1d776cb49c09b09579d9edd0447542970c834.zip | |
target/arm: Handle trapping to EL2 of AArch32 VMRS instructions
HCR_EL2.TID3 requires that AArch32 reads of MVFR[012] are trapped to
EL2, and HCR_EL2.TID0 does the same for reads of FPSID.
In order to handle this, introduce a new TCG helper function that
checks for these control bits before executing the VMRC instruction.
Tested with a hacked-up version of KVM/arm64 that sets the control
bits for 32bit guests.
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20191201122018.25808-4-maz@kernel.org
[PMM: move helper declaration to helper.h; make it
TCG_CALL_NO_WG]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include')
0 files changed, 0 insertions, 0 deletions