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| author | Marcel Apfelbaum | 2017-01-23 20:20:18 +0100 |
|---|---|---|
| committer | Michael S. Tsirkin | 2017-02-01 02:37:17 +0100 |
| commit | 9d5154d753920c56b42a2b6069c0b09d74ad8c06 (patch) | |
| tree | 7064ee2c524bbb69a624cd7fc3b82cb4e3264d7b /include | |
| parent | intel_iommu: fix and simplify size calculation in process_device_iotlb_desc() (diff) | |
| download | qemu-9d5154d753920c56b42a2b6069c0b09d74ad8c06.tar.gz qemu-9d5154d753920c56b42a2b6069c0b09d74ad8c06.tar.xz qemu-9d5154d753920c56b42a2b6069c0b09d74ad8c06.zip | |
hw/pcie: Introduce a base class for PCI Express Root Ports
The 'base' PCI Express Root Port includes
the common code to be re-used for all
Root Ports implementations. Most of the code
was taken from the current implementation
of Intel's IOH 3420 Root Port.
Signed-off-by: Marcel Apfelbaum <marcel@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/hw/pci/pcie_port.h | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/include/hw/pci/pcie_port.h b/include/hw/pci/pcie_port.h index f7b64db00c..13332668e8 100644 --- a/include/hw/pci/pcie_port.h +++ b/include/hw/pci/pcie_port.h @@ -57,4 +57,23 @@ PCIESlot *pcie_chassis_find_slot(uint8_t chassis, uint16_t slot); int pcie_chassis_add_slot(struct PCIESlot *slot); void pcie_chassis_del_slot(PCIESlot *s); +#define TYPE_PCIE_ROOT_PORT "pcie-root-port-base" +#define PCIE_ROOT_PORT_CLASS(klass) \ + OBJECT_CLASS_CHECK(PCIERootPortClass, (klass), TYPE_PCIE_ROOT_PORT) +#define PCIE_ROOT_PORT_GET_CLASS(obj) \ + OBJECT_GET_CLASS(PCIERootPortClass, (obj), TYPE_PCIE_ROOT_PORT) + +typedef struct PCIERootPortClass { + PCIDeviceClass parent_class; + + uint8_t (*aer_vector)(const PCIDevice *dev); + int (*interrupts_init)(PCIDevice *dev, Error **errp); + void (*interrupts_uninit)(PCIDevice *dev); + + int exp_offset; + int aer_offset; + int ssvid_offset; + int ssid; +} PCIERootPortClass; + #endif /* QEMU_PCIE_PORT_H */ |