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| author | Frank Chang | 2022-09-18 10:32:44 +0200 |
|---|---|---|
| committer | Alistair Francis | 2022-09-26 23:04:38 +0200 |
| commit | 9e37653b5c73d8e43013ed78ee9d7644f23d146c (patch) | |
| tree | 002091a33f4987afccfadaf07dc98a848842edb6 /include | |
| parent | hw/riscv: opentitan: Expose the resetvec as a SoC property (diff) | |
| download | qemu-9e37653b5c73d8e43013ed78ee9d7644f23d146c.tar.gz qemu-9e37653b5c73d8e43013ed78ee9d7644f23d146c.tar.xz qemu-9e37653b5c73d8e43013ed78ee9d7644f23d146c.zip | |
target/riscv: Check the correct exception cause in vector GDB stub
After RISCVException enum is introduced, riscv_csrrw_debug() returns
RISCV_EXCP_NONE to indicate there's no error. RISC-V vector GDB stub
should check the result against RISCV_EXCP_NONE instead of value 0.
Otherwise, 'E14' packet would be incorrectly reported for vector CSRs
when using "info reg vector" GDB command.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Tommy Wu <tommy.wu@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-Id: <20220918083245.13028-1-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'include')
0 files changed, 0 insertions, 0 deletions