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| author | Andrew Jones | 2019-03-25 15:16:47 +0100 |
|---|---|---|
| committer | Peter Maydell | 2019-03-25 15:16:47 +0100 |
| commit | a46118fc16537a593119e5b316052a98514046bb (patch) | |
| tree | 36ecb48e61cbb0f79b1684647dfe3f587b95db54 /include | |
| parent | target/arm: fix crash on pmu register access (diff) | |
| download | qemu-a46118fc16537a593119e5b316052a98514046bb.tar.gz qemu-a46118fc16537a593119e5b316052a98514046bb.tar.xz qemu-a46118fc16537a593119e5b316052a98514046bb.zip | |
target/arm: cortex-a7 and cortex-a15 have pmus
cortex-a7 and cortex-a15 have pmus (PMUv2) and they advertise
them in ID_DFR0. Let's allow them to function. This also enables
the pmu cpu property to work with these cpu types, i.e. we can
now do '-cpu cortex-a15,pmu=off' to remove the pmu.
Signed-off-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190322162333.17159-3-drjones@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include')
0 files changed, 0 insertions, 0 deletions