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author | Green Wan | 2020-10-20 05:37:31 +0200 |
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committer | Alistair Francis | 2020-10-22 21:00:46 +0200 |
commit | a54d259157e2575b69e2cf7cf03592c74559cb7e (patch) | |
tree | 4360abfcffc7237a2fc593abec5d58a6c983adff /include | |
parent | target/riscv: raise exception to HS-mode at get_physical_address (diff) | |
download | qemu-a54d259157e2575b69e2cf7cf03592c74559cb7e.tar.gz qemu-a54d259157e2575b69e2cf7cf03592c74559cb7e.tar.xz qemu-a54d259157e2575b69e2cf7cf03592c74559cb7e.zip |
hw/misc/sifive_u_otp: Add write function and write-once protection
- Add write operation to update fuse data bit when PWE bit is on.
- Add array, fuse_wo, to store the 'written' status for all bits
of OTP to block the write operation.
Signed-off-by: Green Wan <green.wan@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Message-id: 20201020033732.12921-2-green.wan@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'include')
-rw-r--r-- | include/hw/misc/sifive_u_otp.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/include/hw/misc/sifive_u_otp.h b/include/hw/misc/sifive_u_otp.h index 82c9176c8f..ebffbc1fa5 100644 --- a/include/hw/misc/sifive_u_otp.h +++ b/include/hw/misc/sifive_u_otp.h @@ -36,6 +36,8 @@ #define SIFIVE_U_OTP_PTRIM 0x34 #define SIFIVE_U_OTP_PWE 0x38 +#define SIFIVE_U_OTP_PWE_EN (1 << 0) + #define SIFIVE_U_OTP_PCE_EN (1 << 0) #define SIFIVE_U_OTP_PDSTB_EN (1 << 0) @@ -75,6 +77,7 @@ struct SiFiveUOTPState { uint32_t ptrim; uint32_t pwe; uint32_t fuse[SIFIVE_U_OTP_NUM_FUSES]; + uint32_t fuse_wo[SIFIVE_U_OTP_NUM_FUSES]; /* config */ uint32_t serial; }; |