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| author | Joel Stanley | 2018-06-15 15:57:15 +0200 |
|---|---|---|
| committer | Peter Maydell | 2018-06-15 16:23:34 +0200 |
| commit | acd9575e59da1bfc21a1feccb00c5dddd45328f7 (patch) | |
| tree | 38d5dfee59be8fcecd839cb8b85c7c55dc46680b /include | |
| parent | target/arm: Implement SVE Floating Point Arithmetic - Unpredicated Group (diff) | |
| download | qemu-acd9575e59da1bfc21a1feccb00c5dddd45328f7.tar.gz qemu-acd9575e59da1bfc21a1feccb00c5dddd45328f7.tar.xz qemu-acd9575e59da1bfc21a1feccb00c5dddd45328f7.zip | |
aspeed_scu: Implement RNG register
The ASPEED SoCs contain a single register that returns random data when
read. This models that register so that guests can use it.
The random number data register has a corresponding control register,
however it returns data regardless of the state of the enabled bit, so
the model follows this behaviour.
When the qcrypto call fails we exit as the guest uses the random number
device to feed it's entropy pool, which is used for cryptographic
purposes.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Message-id: 20180613114836.9265-1-joel@jms.id.au
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include')
0 files changed, 0 insertions, 0 deletions