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| author | Richard Henderson | 2018-10-03 18:32:09 +0200 |
|---|---|---|
| committer | Richard Henderson | 2018-10-05 19:57:41 +0200 |
| commit | b299e88d4261b0af30190e74005ad930e04f3a11 (patch) | |
| tree | 15938c066b3db9497b43603d6275cc7cf6b7fbaf /include | |
| parent | softfloat: Fix division (diff) | |
| download | qemu-b299e88d4261b0af30190e74005ad930e04f3a11.tar.gz qemu-b299e88d4261b0af30190e74005ad930e04f3a11.tar.xz qemu-b299e88d4261b0af30190e74005ad930e04f3a11.zip | |
softfloat: Specialize udiv_qrnnd for x86_64
The ISA has a 128/64-bit division instruction.
Tested-by: Emilio G. Cota <cota@braap.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/fpu/softfloat-macros.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/include/fpu/softfloat-macros.h b/include/fpu/softfloat-macros.h index a1d99c730d..39eb08b4f1 100644 --- a/include/fpu/softfloat-macros.h +++ b/include/fpu/softfloat-macros.h @@ -637,6 +637,11 @@ static inline uint64_t estimateDiv128To64(uint64_t a0, uint64_t a1, uint64_t b) static inline uint64_t udiv_qrnnd(uint64_t *r, uint64_t n1, uint64_t n0, uint64_t d) { +#if defined(__x86_64__) + uint64_t q; + asm("divq %4" : "=a"(q), "=d"(*r) : "0"(n0), "1"(n1), "rm"(d)); + return q; +#else uint64_t d0, d1, q0, q1, r1, r0, m; d0 = (uint32_t)d; @@ -676,6 +681,7 @@ static inline uint64_t udiv_qrnnd(uint64_t *r, uint64_t n1, *r = r0; return (q1 << 32) | q0; +#endif } /*---------------------------------------------------------------------------- |