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| author | Peter Maydell | 2019-02-01 15:55:43 +0100 |
|---|---|---|
| committer | Peter Maydell | 2019-02-01 15:55:43 +0100 |
| commit | c1f572579eefe18e56c7135e2a7c0698f0488b92 (patch) | |
| tree | 8801e2836536769684bca755f16e8c9c073f61f5 /include | |
| parent | hw/arm/armsse: Add unimplemented-device stub for cache control registers (diff) | |
| download | qemu-c1f572579eefe18e56c7135e2a7c0698f0488b92.tar.gz qemu-c1f572579eefe18e56c7135e2a7c0698f0488b92.tar.xz qemu-c1f572579eefe18e56c7135e2a7c0698f0488b92.zip | |
hw/arm/armsse: Add unimplemented-device stub for CPU local control registers
The SSE-200 has a "CPU local security control" register bank; add an
unimplemented-device stub for it. (The register bank has only one
interesting register, which allows the guest to lock down changes
to various CPU registers so they cannot be modified further. We
don't support that in our Cortex-M33 model anyway.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190121185118.18550-19-peter.maydell@linaro.org
Diffstat (limited to 'include')
| -rw-r--r-- | include/hw/arm/armsse.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index 9d830057d5..961dbb3032 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -151,6 +151,7 @@ typedef struct ARMSSE { UnimplementedDeviceState mhu[2]; UnimplementedDeviceState ppu[NUM_PPUS]; UnimplementedDeviceState cachectrl[SSE_MAX_CPUS]; + UnimplementedDeviceState cpusecctrl[SSE_MAX_CPUS]; /* * 'container' holds all devices seen by all CPUs. |