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| author | Peter Maydell | 2021-02-18 17:33:36 +0100 |
|---|---|---|
| committer | Peter Maydell | 2021-02-18 17:33:36 +0100 |
| commit | c79f01c9450bcf90c08a77f13fbf67bdba59a316 (patch) | |
| tree | aed02be84b9b5caffdaa4ad28655e814724eafd7 /include | |
| parent | Merge remote-tracking branch 'remotes/kraxel/tags/usb-20210218-pull-request' ... (diff) | |
| parent | Hexagon build infrastructure (diff) | |
| download | qemu-c79f01c9450bcf90c08a77f13fbf67bdba59a316.tar.gz qemu-c79f01c9450bcf90c08a77f13fbf67bdba59a316.tar.xz qemu-c79f01c9450bcf90c08a77f13fbf67bdba59a316.zip | |
Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-hex-20210218' into staging
Initial commit for the Qualcomm Hexagon processor.
# gpg: Signature made Thu 18 Feb 2021 16:26:52 GMT
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* remotes/rth-gitlab/tags/pull-hex-20210218: (35 commits)
Hexagon build infrastructure
Hexagon (tests/tcg/hexagon) TCG tests - floating point
Hexagon (tests/tcg/hexagon) TCG tests - atomics/load/store/misc
Hexagon (tests/tcg/hexagon) TCG tests - multiarch
Hexagon (linux-user/hexagon) Linux user emulation
Hexagon (target/hexagon) translation
Hexagon (target/hexagon) TCG for floating point instructions
Hexagon (target/hexagon) TCG for instructions with multiple definitions
Hexagon (target/hexagon) TCG generation
Hexagon (target/hexagon) instruction classes
Hexagon (target/hexagon) macros
Hexagon (target/hexagon) opcode data structures
Hexagon (target/hexagon) generater phase 4 - decode tree
Hexagon (target/hexagon) generator phase 3 - C preprocessor for decode tree
Hexagon (target/hexagon) generator phase 2 - generate header files
Hexagon (target/hexagon) generator phase 1 - C preprocessor for semantics
Hexagon (target/hexagon/imported) arch import
Hexagon (target/hexagon/fma_emu.[ch]) utility functions
Hexagon (target/hexagon/conv_emu.[ch]) utility functions
Hexagon (target/hexagon/arch.[ch]) utility functions
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/disas/dis-asm.h | 1 | ||||
| -rw-r--r-- | include/elf.h | 1 | ||||
| -rw-r--r-- | include/qemu/int128.h | 10 |
3 files changed, 12 insertions, 0 deletions
diff --git a/include/disas/dis-asm.h b/include/disas/dis-asm.h index d1133a4e04..13fa1edd41 100644 --- a/include/disas/dis-asm.h +++ b/include/disas/dis-asm.h @@ -459,6 +459,7 @@ int print_insn_xtensa (bfd_vma, disassemble_info*); int print_insn_riscv32 (bfd_vma, disassemble_info*); int print_insn_riscv64 (bfd_vma, disassemble_info*); int print_insn_rx(bfd_vma, disassemble_info *); +int print_insn_hexagon(bfd_vma, disassemble_info *); #ifdef CONFIG_CAPSTONE bool cap_disas_target(disassemble_info *info, uint64_t pc, size_t size); diff --git a/include/elf.h b/include/elf.h index 7a418ee559..f4fa3c1cd4 100644 --- a/include/elf.h +++ b/include/elf.h @@ -176,6 +176,7 @@ typedef struct mips_elf_abiflags_v0 { #define EM_UNICORE32 110 /* UniCore32 */ +#define EM_HEXAGON 164 /* Qualcomm Hexagon */ #define EM_RX 173 /* Renesas RX family */ #define EM_RISCV 243 /* RISC-V */ diff --git a/include/qemu/int128.h b/include/qemu/int128.h index 76ea405922..52fc238421 100644 --- a/include/qemu/int128.h +++ b/include/qemu/int128.h @@ -58,6 +58,11 @@ static inline Int128 int128_and(Int128 a, Int128 b) return a & b; } +static inline Int128 int128_or(Int128 a, Int128 b) +{ + return a | b; +} + static inline Int128 int128_rshift(Int128 a, int n) { return a >> n; @@ -208,6 +213,11 @@ static inline Int128 int128_and(Int128 a, Int128 b) return (Int128) { a.lo & b.lo, a.hi & b.hi }; } +static inline Int128 int128_or(Int128 a, Int128 b) +{ + return (Int128) { a.lo | b.lo, a.hi | b.hi }; +} + static inline Int128 int128_rshift(Int128 a, int n) { int64_t h; |