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| author | Alex Bennée | 2018-05-02 16:58:31 +0200 |
|---|---|---|
| committer | Richard Henderson | 2018-05-18 00:27:15 +0200 |
| commit | ca3a3d5a3141d44aa717dc11e4d33a834a85e1f6 (patch) | |
| tree | 65072b8909749f2dfccdb6b0ec7c57fcba4e5e0c /include | |
| parent | target/arm: squash FZ16 behaviour for conversions (diff) | |
| download | qemu-ca3a3d5a3141d44aa717dc11e4d33a834a85e1f6.tar.gz qemu-ca3a3d5a3141d44aa717dc11e4d33a834a85e1f6.tar.xz qemu-ca3a3d5a3141d44aa717dc11e4d33a834a85e1f6.zip | |
fpu/softfloat: Partial support for ARM Alternative half-precision
For float16 ARM supports an alternative half-precision format which
sacrifices the ability to represent NaN/Inf in return for a higher
dynamic range. The new FloatFmt flag, arm_althp, is then used to
modify the behaviour of canonicalize and round_canonical with respect
to representation and exception raising.
Usage of this new flag waits until we re-factor float-to-float conversions.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'include')
0 files changed, 0 insertions, 0 deletions