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| author | Peter Maydell | 2018-08-24 14:17:47 +0200 |
|---|---|---|
| committer | Peter Maydell | 2018-08-24 14:17:47 +0200 |
| commit | cb159db944b290a4704603baa8b96facde634521 (patch) | |
| tree | 42a9a8f70c1fa6beba523aab08f222c808795adc /include | |
| parent | hw/arm/mps2-tz: Instantiate SPI controllers (diff) | |
| download | qemu-cb159db944b290a4704603baa8b96facde634521.tar.gz qemu-cb159db944b290a4704603baa8b96facde634521.tar.xz qemu-cb159db944b290a4704603baa8b96facde634521.zip | |
hw/arm/mps2-tz: Fix MPS2 SCC config register values
Some of the config register values we were setting for the MPS2 SCC
weren't correct:
* the SCC_AID bits [23:20] specify the FPGA build target board revision,
and the SCC_CFG4 register specifies the actual board revision, so
these should have matching values. Claim to be board revision C,
consistently -- we had the revision in the wrong part of SCC_AID.
* SCC_ID bits [15:4] should be 0x505, not decimal 505
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20180820141116.9118-23-peter.maydell@linaro.org
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'include')
0 files changed, 0 insertions, 0 deletions