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| author | Mark Cave-Ayland | 2021-03-04 23:10:53 +0100 |
|---|---|---|
| committer | Mark Cave-Ayland | 2021-03-07 11:39:05 +0100 |
| commit | cf47a41e055f6f90a2cecdb9eb3c4cebfde23f2a (patch) | |
| tree | 4056e608d4143a50c17c011c178d7e2e0a3d760e /include | |
| parent | esp: implement FIFO flush command (diff) | |
| download | qemu-cf47a41e055f6f90a2cecdb9eb3c4cebfde23f2a.tar.gz qemu-cf47a41e055f6f90a2cecdb9eb3c4cebfde23f2a.tar.xz qemu-cf47a41e055f6f90a2cecdb9eb3c4cebfde23f2a.zip | |
esp: latch individual bits in ESP_RINTR register
Currently the ESP_RINTR register is set to a specific value as required within
the ESP state machine. In order to implement the upcoming deferred interrupt
functionality it is necessary to set individual bits within ESP_RINTR so that
a deferred interrupt will not overwrite the value of any other interrupt bits.
This also requires fixing up a few locations where the ESP_RINTR and ESP_RSEQ
registers are set/reset unexpectedly.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Message-Id: <20210304221103.6369-33-mark.cave-ayland@ilande.co.uk>
Diffstat (limited to 'include')
0 files changed, 0 insertions, 0 deletions