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| author | Bin Meng | 2019-09-06 18:20:00 +0200 |
|---|---|---|
| committer | Palmer Dabbelt | 2019-09-17 17:42:46 +0200 |
| commit | d0730344fd8f27ce5e98efd43efe594ae3a00087 (patch) | |
| tree | 49354c614249153a146acb31a677c9f717055abf /include | |
| parent | riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming (diff) | |
| download | qemu-d0730344fd8f27ce5e98efd43efe594ae3a00087.tar.gz qemu-d0730344fd8f27ce5e98efd43efe594ae3a00087.tar.xz qemu-d0730344fd8f27ce5e98efd43efe594ae3a00087.zip | |
riscv: sifive_e: prci: Update the PRCI register block size
Currently the PRCI register block size is set to 0x8000, but in fact
0x1000 is enough, which is also what the manual says.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Chih-Min Chao <chihmin.chao@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/hw/riscv/sifive_e_prci.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/hw/riscv/sifive_e_prci.h b/include/hw/riscv/sifive_e_prci.h index c4b76aa17a..698b0b451c 100644 --- a/include/hw/riscv/sifive_e_prci.h +++ b/include/hw/riscv/sifive_e_prci.h @@ -47,6 +47,8 @@ enum { SIFIVE_E_PRCI_PLLOUTDIV_DIV1 = (1 << 8) }; +#define SIFIVE_E_PRCI_REG_SIZE 0x1000 + #define TYPE_SIFIVE_E_PRCI "riscv.sifive.e.prci" #define SIFIVE_E_PRCI(obj) \ |