diff options
| author | Alistair Francis | 2020-12-16 19:22:32 +0100 |
|---|---|---|
| committer | Alistair Francis | 2020-12-18 06:56:44 +0100 |
| commit | dc4d4aaee31cd3ac4020d3b15729f0a104ce8862 (patch) | |
| tree | 0aac58cd39025f1e44a1f366a1c2e4386d7b8347 /include | |
| parent | target/riscv: Add a TYPE_RISCV_CPU_BASE CPU (diff) | |
| download | qemu-dc4d4aaee31cd3ac4020d3b15729f0a104ce8862.tar.gz qemu-dc4d4aaee31cd3ac4020d3b15729f0a104ce8862.tar.xz qemu-dc4d4aaee31cd3ac4020d3b15729f0a104ce8862.zip | |
riscv: spike: Remove target macro conditionals
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
Message-id: 04ac7fba2348c92f296a5e6a9959ac72b77ae4c6.1608142916.git.alistair.francis@wdc.com
Diffstat (limited to 'include')
| -rw-r--r-- | include/hw/riscv/spike.h | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/include/hw/riscv/spike.h b/include/hw/riscv/spike.h index cddeca2e77..cdd1a13011 100644 --- a/include/hw/riscv/spike.h +++ b/include/hw/riscv/spike.h @@ -47,10 +47,4 @@ enum { SPIKE_DRAM }; -#if defined(TARGET_RISCV32) -#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_BASE32 -#elif defined(TARGET_RISCV64) -#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_BASE64 -#endif - #endif |