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| author | Peter Maydell | 2020-02-10 13:01:46 +0100 |
|---|---|---|
| committer | Peter Maydell | 2020-02-13 15:30:51 +0100 |
| commit | dc7a88d0810ad272bdcd2e0869359af78fdd9114 (patch) | |
| tree | 9a4c94c9e41811cddbf7a6318e26e6787260e4f2 /include | |
| parent | hw/arm/raspi: Extract the cores count from the board revision (diff) | |
| download | qemu-dc7a88d0810ad272bdcd2e0869359af78fdd9114.tar.gz qemu-dc7a88d0810ad272bdcd2e0869359af78fdd9114.tar.xz qemu-dc7a88d0810ad272bdcd2e0869359af78fdd9114.zip | |
target/arm: Implement ARMv8.1-VMID16 extension
The ARMv8.1-VMID16 extension extends the VMID from 8 bits to 16 bits:
* the ID_AA64MMFR1_EL1.VMIDBits field specifies whether the VMID is
8 or 16 bits
* the VMID field in VTTBR_EL2 is extended to 16 bits
* VTCR_EL2.VS lets the guest specify whether to use the full 16 bits,
or use the backwards-compatible 8 bits
For QEMU implementing this is trivial:
* we do not track VMIDs in TLB entries, so we never use the VMID field
* we treat any write to VTTBR_EL2, not just a change to the VMID field
bits, as a "possible VMID change" that causes us to throw away TLB
entries, so that code doesn't need changing
* we allow the guest to read/write the VTCR_EL2.VS bit already
So all that's missing is the ID register part: report that we support
VMID16 in our 'max' CPU.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200210120146.17631-1-peter.maydell@linaro.org
Diffstat (limited to 'include')
0 files changed, 0 insertions, 0 deletions
