diff options
| author | Xiaojuan Yang | 2022-07-05 08:49:00 +0200 |
|---|---|---|
| committer | Richard Henderson | 2022-07-05 12:55:17 +0200 |
| commit | ddf93261847df55137436abe429aae7f9d8228dd (patch) | |
| tree | df643314296f894d227ac269bfac43ec7df7d037 /include | |
| parent | tcg/tci: Remove CONFIG_DEBUG_TCG_INTERPRETER (diff) | |
| download | qemu-ddf93261847df55137436abe429aae7f9d8228dd.tar.gz qemu-ddf93261847df55137436abe429aae7f9d8228dd.tar.xz qemu-ddf93261847df55137436abe429aae7f9d8228dd.zip | |
hw/intc/loongarch_ipi: Fix ipi device access of 64bits
In general loongarch ipi device, 32bit registers is emulated, however for
anysend/mailsend device only 64bit register access is supported. So separate
the ipi memory region into two regions, including 32 bits and 64 bits.
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Message-Id: <20220705064901.2353349-2-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/hw/intc/loongarch_ipi.h | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/include/hw/intc/loongarch_ipi.h b/include/hw/intc/loongarch_ipi.h index 996ed7ea93..0ee48fca55 100644 --- a/include/hw/intc/loongarch_ipi.h +++ b/include/hw/intc/loongarch_ipi.h @@ -24,8 +24,9 @@ #define IOCSR_MAIL_SEND 0x48 #define IOCSR_ANY_SEND 0x158 -/* IPI system memory address */ -#define IPI_SYSTEM_MEM 0x1fe01000 +#define MAIL_SEND_ADDR (SMP_IPI_MAILBOX + IOCSR_MAIL_SEND) +#define MAIL_SEND_OFFSET 0 +#define ANY_SEND_OFFSET (IOCSR_ANY_SEND - IOCSR_MAIL_SEND) #define MAX_IPI_CORE_NUM 4 #define MAX_IPI_MBX_NUM 4 @@ -46,7 +47,7 @@ typedef struct IPICore { struct LoongArchIPI { SysBusDevice parent_obj; MemoryRegion ipi_iocsr_mem[MAX_IPI_CORE_NUM]; - MemoryRegion ipi_system_mem[MAX_IPI_CORE_NUM]; + MemoryRegion ipi64_iocsr_mem[MAX_IPI_CORE_NUM]; }; #endif |