diff options
| author | Peter Maydell | 2019-02-01 15:55:42 +0100 |
|---|---|---|
| committer | Peter Maydell | 2019-02-01 15:55:42 +0100 |
| commit | f0cab7fe88e1751209d6f3d8b9bac04b09b2e7ea (patch) | |
| tree | 3d46a5eef03ad05a1a85105509c07ca153733bfb /include | |
| parent | hw/misc/iotkit-secctl: Support 4 internal MPCs (diff) | |
| download | qemu-f0cab7fe88e1751209d6f3d8b9bac04b09b2e7ea.tar.gz qemu-f0cab7fe88e1751209d6f3d8b9bac04b09b2e7ea.tar.xz qemu-f0cab7fe88e1751209d6f3d8b9bac04b09b2e7ea.zip | |
hw/arm/armsse: Make number of SRAM banks parameterised
The SSE-200 has four banks of SRAM, each with its own
Memory Protection Controller, where the IoTKit has only one.
Make the number of SRAM banks a field in ARMSSEInfo.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190121185118.18550-10-peter.maydell@linaro.org
Diffstat (limited to 'include')
| -rw-r--r-- | include/hw/arm/armsse.h | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index ff51205498..99714aa63c 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -90,6 +90,11 @@ #define NUM_EXTERNAL_PPCS (IOTS_NUM_AHB_EXP_PPC + IOTS_NUM_APB_EXP_PPC) #define NUM_PPCS (NUM_EXTERNAL_PPCS + 2) +#define MAX_SRAM_BANKS 4 +#if MAX_SRAM_BANKS > IOTS_NUM_MPC +#error Too many SRAM banks +#endif + typedef struct ARMSSE { /*< private >*/ SysBusDevice parent_obj; @@ -99,7 +104,7 @@ typedef struct ARMSSE { IoTKitSecCtl secctl; TZPPC apb_ppc0; TZPPC apb_ppc1; - TZMPC mpc; + TZMPC mpc[IOTS_NUM_MPC]; CMSDKAPBTIMER timer0; CMSDKAPBTIMER timer1; CMSDKAPBTIMER s32ktimer; @@ -123,7 +128,7 @@ typedef struct ARMSSE { MemoryRegion alias1; MemoryRegion alias2; MemoryRegion alias3; - MemoryRegion sram0; + MemoryRegion sram[MAX_SRAM_BANKS]; qemu_irq *exp_irqs; qemu_irq ppc0_irq; |