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| author | Peter Maydell | 2022-09-23 14:34:12 +0200 |
|---|---|---|
| committer | Peter Maydell | 2022-09-29 18:31:52 +0200 |
| commit | f190bd1da1c291bb1dac9a715e02ef2521698d16 (patch) | |
| tree | b746450a40deccef538ea23f59da3ecda6e25be2 /include | |
| parent | target/arm: Make writes to MDCR_EL3 use PMU start/finish calls (diff) | |
| download | qemu-f190bd1da1c291bb1dac9a715e02ef2521698d16.tar.gz qemu-f190bd1da1c291bb1dac9a715e02ef2521698d16.tar.xz qemu-f190bd1da1c291bb1dac9a715e02ef2521698d16.zip | |
target/arm: Update SDCR_VALID_MASK to include SCCD
Our SDCR_VALID_MASK doesn't include all of the bits which are defined
by the current architecture. In particular in commit 0b42f4fab9d3 we
forgot to add SCCD, which meant that an AArch32 guest couldn't
actually use the SCCD bit to disable counting in Secure state.
Add all the currently defined bits; we don't implement all of them,
but this makes them be reads-as-written, which is architecturally
valid and matches how we currently handle most of the others in the
mask.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220923123412.1214041-4-peter.maydell@linaro.org
Diffstat (limited to 'include')
0 files changed, 0 insertions, 0 deletions