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| author | Alistair Francis | 2021-08-30 07:35:02 +0200 |
|---|---|---|
| committer | Alistair Francis | 2021-09-20 23:56:49 +0200 |
| commit | f436ecc3156dea7edce97e7c247e3667203f5c8b (patch) | |
| tree | 1ca775b95bfaa3f19cb76a7cff031ac9aa05c4e0 /include | |
| parent | hw/intc: ibex_plic: Convert the PLIC to use RISC-V CPU GPIO lines (diff) | |
| download | qemu-f436ecc3156dea7edce97e7c247e3667203f5c8b.tar.gz qemu-f436ecc3156dea7edce97e7c247e3667203f5c8b.tar.xz qemu-f436ecc3156dea7edce97e7c247e3667203f5c8b.zip | |
hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO lines
Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V
CPU GPIO lines to set the external MIP bits.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 0364190bfa935058a845c0fa1ecf650328840ad5.1630301632.git.alistair.francis@wdc.com
Diffstat (limited to 'include')
| -rw-r--r-- | include/hw/intc/sifive_plic.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/include/hw/intc/sifive_plic.h b/include/hw/intc/sifive_plic.h index 1e451a270c..134cf39a96 100644 --- a/include/hw/intc/sifive_plic.h +++ b/include/hw/intc/sifive_plic.h @@ -72,9 +72,13 @@ struct SiFivePLICState { uint32_t context_base; uint32_t context_stride; uint32_t aperture_size; + + qemu_irq *m_external_irqs; + qemu_irq *s_external_irqs; }; DeviceState *sifive_plic_create(hwaddr addr, char *hart_config, + uint32_t num_harts, uint32_t hartid_base, uint32_t num_sources, uint32_t num_priorities, uint32_t priority_base, uint32_t pending_base, uint32_t enable_base, |