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| author | Andrew Jeffery | 2017-09-04 16:21:54 +0200 |
|---|---|---|
| committer | Peter Maydell | 2017-09-04 16:21:54 +0200 |
| commit | f55d613bc97cd8d08487eddec313c3298a906a91 (patch) | |
| tree | da46c15c3b8a14e1d174810ad95d2d8e2e95fcfa /include | |
| parent | target/arm/kvm: pmu: improve error handling (diff) | |
| download | qemu-f55d613bc97cd8d08487eddec313c3298a906a91.tar.gz qemu-f55d613bc97cd8d08487eddec313c3298a906a91.tar.xz qemu-f55d613bc97cd8d08487eddec313c3298a906a91.zip | |
watchdog: wdt_aspeed: Add support for the reset width register
The reset width register controls how the pulse on the SoC's WDTRST{1,2}
pins behaves. A pulse is emitted if the external reset bit is set in
WDT_CTRL. On the AST2500 WDT_RESET_WIDTH can consume magic bit patterns
to configure push-pull/open-drain and active-high/active-low
behaviours and thus needs some special handling in the write path.
As some of the capabilities depend on the SoC version a silicon-rev
property is introduced, which is used to guard version-specific
behaviour.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/hw/watchdog/wdt_aspeed.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/hw/watchdog/wdt_aspeed.h b/include/hw/watchdog/wdt_aspeed.h index 080c223122..7de3e5c224 100644 --- a/include/hw/watchdog/wdt_aspeed.h +++ b/include/hw/watchdog/wdt_aspeed.h @@ -27,6 +27,8 @@ typedef struct AspeedWDTState { uint32_t regs[ASPEED_WDT_REGS_MAX]; uint32_t pclk_freq; + uint32_t silicon_rev; + uint32_t ext_pulse_width_mask; } AspeedWDTState; #endif /* ASPEED_WDT_H */ |