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| author | Marc Zyngier | 2019-12-01 13:20:18 +0100 |
|---|---|---|
| committer | Peter Maydell | 2019-12-16 11:46:35 +0100 |
| commit | f96f3d5f09973ef40f164cf2d5fd98ce5498b82a (patch) | |
| tree | ec0f0f500fce06f3dc358f71d59bb2910b6bb565 /include | |
| parent | target/arm: Handle AArch32 CP15 trapping via HSTR_EL2 (diff) | |
| download | qemu-f96f3d5f09973ef40f164cf2d5fd98ce5498b82a.tar.gz qemu-f96f3d5f09973ef40f164cf2d5fd98ce5498b82a.tar.xz qemu-f96f3d5f09973ef40f164cf2d5fd98ce5498b82a.zip | |
target/arm: Add support for missing Jazelle system registers
QEMU lacks the minimum Jazelle implementation that is required
by the architecture (everything is RAZ or RAZ/WI). Add it
together with the HCR_EL2.TID0 trapping that goes with it.
Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20191201122018.25808-6-maz@kernel.org
[PMM: moved ARMCPRegInfo array to file scope, marked it
'static global', moved new condition down in
register_cp_regs_for_features() to go with other feature
things rather than up with the v6/v7/v8 stuff]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include')
0 files changed, 0 insertions, 0 deletions