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| author | Alistair Francis | 2020-03-03 00:08:51 +0100 |
|---|---|---|
| committer | Alistair Francis | 2020-04-29 22:16:36 +0200 |
| commit | fda5b000faf401cf595c4e87809eac3378ddbfd4 (patch) | |
| tree | 6cc37ee44bcdd021efe17eff745b17b13a4679f8 /include | |
| parent | riscv/sifive_u: Fix up file ordering (diff) | |
| download | qemu-fda5b000faf401cf595c4e87809eac3378ddbfd4.tar.gz qemu-fda5b000faf401cf595c4e87809eac3378ddbfd4.tar.xz qemu-fda5b000faf401cf595c4e87809eac3378ddbfd4.zip | |
riscv/sifive_u: Add a serial property to the sifive_u SoC
At present the board serial number is hard-coded to 1, and passed
to OTP model during initialization. Firmware (FSBL, U-Boot) uses
the serial number to generate a unique MAC address for the on-chip
ethernet controller. When multiple QEMU 'sifive_u' instances are
created and connected to the same subnet, they all have the same
MAC address hence it creates a unusable network.
A new "serial" property is introduced to the sifive_u SoC to specify
the board serial number. When not given, the default serial number
1 is used.
Suggested-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/hw/riscv/sifive_u.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 82667b5746..a2baa1de5f 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -42,6 +42,8 @@ typedef struct SiFiveUSoCState { SiFiveUPRCIState prci; SiFiveUOTPState otp; CadenceGEMState gem; + + uint32_t serial; } SiFiveUSoCState; #define TYPE_RISCV_U_MACHINE MACHINE_TYPE_NAME("sifive_u") |