diff options
| author | Anup Patel | 2018-12-13 19:34:52 +0100 |
|---|---|---|
| committer | Palmer Dabbelt | 2018-12-20 21:03:12 +0100 |
| commit | fe93582cf52ee67f6ab5a59051d354344010cfdc (patch) | |
| tree | 66f3c96a1164eb8ac47bfc9314904d79440924dd /include | |
| parent | riscv: Enable VGA and PCIE_VGA (diff) | |
| download | qemu-fe93582cf52ee67f6ab5a59051d354344010cfdc.tar.gz qemu-fe93582cf52ee67f6ab5a59051d354344010cfdc.tar.xz qemu-fe93582cf52ee67f6ab5a59051d354344010cfdc.zip | |
sifive_u: Add clock DT node for GEM ethernet
The GEM ethernet on SiFive unleashed has fixed input clock
of 125MHz as-per SiFive FU540 manual. This patch updates FDT
generation for QEMU sifive_u machine to provide fixed-rate
clock for GEM ethernet.
Signed-off-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/hw/riscv/sifive_u.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index e8b4d9ffa3..be13cc1304 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -63,7 +63,8 @@ enum { }; enum { - SIFIVE_U_CLOCK_FREQ = 1000000000 + SIFIVE_U_CLOCK_FREQ = 1000000000, + SIFIVE_U_GEM_CLOCK_FREQ = 125000000 }; #define SIFIVE_U_PLIC_HART_CONFIG "MS" |