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| author | Yongbok Kim | 2016-03-15 10:59:28 +0100 |
|---|---|---|
| committer | Leon Alrae | 2016-03-30 10:13:59 +0200 |
| commit | 3994215db442e11880cfd0c337137d6dcf56e11d (patch) | |
| tree | ecce721b4211323b7343e97667ae42f3253f855b /iohandler.c | |
| parent | target-mips: add CMGCRBase register (diff) | |
| download | qemu-3994215db442e11880cfd0c337137d6dcf56e11d.tar.gz qemu-3994215db442e11880cfd0c337137d6dcf56e11d.tar.xz qemu-3994215db442e11880cfd0c337137d6dcf56e11d.zip | |
hw/mips: add initial Global Config Register support
Add initial GCR support to indicate number of VPs present in the system,
L2 bypass mode and revision number.
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
[leon.alrae@imgtec.com:
* removed GIC part,
* changed commit message,
* replaced %lx format spec. with PRIx64,
* renamed mips_gcr.{c,h} to mips_cmgcr.{c,h},
* replaced CONFIG_MIPS_GIC with CONFIG_MIPS_CPS]
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Diffstat (limited to 'iohandler.c')
0 files changed, 0 insertions, 0 deletions