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| author | Peter Maydell | 2015-09-18 13:55:27 +0200 |
|---|---|---|
| committer | Peter Maydell | 2015-09-18 13:55:27 +0200 |
| commit | 3bf1f5ec6a7ec8ee06c95bf308d213ebaa129ee0 (patch) | |
| tree | 30c2e51a383243a8d135465729a43b0c2745d94f /linux-headers/linux | |
| parent | target-cris: update CPU state save/load to use VMStateDescription (diff) | |
| parent | target-mips: improve exception handling (diff) | |
| download | qemu-3bf1f5ec6a7ec8ee06c95bf308d213ebaa129ee0.tar.gz qemu-3bf1f5ec6a7ec8ee06c95bf308d213ebaa129ee0.tar.xz qemu-3bf1f5ec6a7ec8ee06c95bf308d213ebaa129ee0.zip | |
Merge remote-tracking branch 'remotes/lalrae/tags/mips-20150918' into staging
MIPS patches 2015-09-18
Changes:
* fixes for rdhwr, tlbwr, mtc0, recip.fmt, rsqrt.fmt and daui instructions
* removal of MIPS_DEBUG code
* use tcg_gen_extrh_i64_i32()
* improve random tlb index generation in cpu_mips_get_random()
* exception handling improvements to correctly restore icount
# gpg: Signature made Fri 18 Sep 2015 12:15:28 BST using RSA key ID 0B29DA6B
# gpg: Good signature from "Leon Alrae <leon.alrae@imgtec.com>"
* remotes/lalrae/tags/mips-20150918:
target-mips: improve exception handling
target-mips: correct MTC0 instruction on MIPS64
target-mips: add missing restriction in DAUI instruction
target-mips: fix corner case in TLBWR causing QEMU to hang
pic32: use LCG algorithm for generated random index of TLBWR instruction
target-mips: get rid of MIPS_DEBUG_SIGN_EXTENSIONS
target-mips: get rid of MIPS_DEBUG
target-mips: Fix RDHWR on CP0.Count
target-mips: remove wrong checks for recip.fmt and rsqrt.fmt
target-mips: Use tcg_gen_extrh_i64_i32
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'linux-headers/linux')
0 files changed, 0 insertions, 0 deletions