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| author | Richard Henderson | 2018-03-09 18:09:43 +0100 |
|---|---|---|
| committer | Peter Maydell | 2018-03-09 18:09:43 +0100 |
| commit | 85fc716732bc6e85a634335847999f411269f282 (patch) | |
| tree | 15ae6a9a0e2d85baa27d03c67af20b749fd9be6c /linux-user/aarch64 | |
| parent | Implement support for i.MX7 Sabre board (diff) | |
| download | qemu-85fc716732bc6e85a634335847999f411269f282.tar.gz qemu-85fc716732bc6e85a634335847999f411269f282.tar.xz qemu-85fc716732bc6e85a634335847999f411269f282.zip | |
linux-user: Implement aarch64 PR_SVE_SET/GET_VL
As an implementation choice, widening VL has zeroed the
previously inaccessible portion of the sve registers.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20180303143823.27055-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'linux-user/aarch64')
| -rw-r--r-- | linux-user/aarch64/target_syscall.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/linux-user/aarch64/target_syscall.h b/linux-user/aarch64/target_syscall.h index 604ab99b14..205265e619 100644 --- a/linux-user/aarch64/target_syscall.h +++ b/linux-user/aarch64/target_syscall.h @@ -19,4 +19,7 @@ struct target_pt_regs { #define TARGET_MLOCKALL_MCL_CURRENT 1 #define TARGET_MLOCKALL_MCL_FUTURE 2 +#define TARGET_PR_SVE_SET_VL 50 +#define TARGET_PR_SVE_GET_VL 51 + #endif /* AARCH64_TARGET_SYSCALL_H */ |