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| author | aurel32 | 2008-09-05 21:07:53 +0200 |
|---|---|---|
| committer | aurel32 | 2008-09-05 21:07:53 +0200 |
| commit | 29d26d20e5b4a9f28cdd9d072b407223e7b0e610 (patch) | |
| tree | f6282aba8ca4adde082eea23ec2811d9f3975aaf /linux-user/arm/nwfpe | |
| parent | CRIS: Mask off the cache selection bit after MMU translations. (diff) | |
| download | qemu-29d26d20e5b4a9f28cdd9d072b407223e7b0e610.tar.gz qemu-29d26d20e5b4a9f28cdd9d072b407223e7b0e610.tar.xz qemu-29d26d20e5b4a9f28cdd9d072b407223e7b0e610.zip | |
fix alpha cmovxx instruction
The CMOV instruction is defined by the alpha manual as:
CMOVxx Ra.rq,Rb.rq,Rc.wq !Operate format
CMOVxx Ra.rq,#b.ib,Rc.wq !Operate format
Operation:
IF TEST(Rav, Condition_based_on_Opcode) THEN
Rc ← Rbv
The current qemu behavior inverses Ra and Rb. This is fixed by this
patch.
Signed-off-by: Tristan Gingold <gingold@adacore.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5171 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'linux-user/arm/nwfpe')
0 files changed, 0 insertions, 0 deletions