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| author | Leon Alrae | 2014-09-11 17:28:17 +0200 |
|---|---|---|
| committer | Leon Alrae | 2015-06-12 10:05:31 +0200 |
| commit | 5204ea79ea739b557f47fc4db96c94edcb33a5d6 (patch) | |
| tree | 6b439e0077f4624a23b47ec81770e4debda4cf9c /linux-user/elfload.c | |
| parent | target-mips: add CP0.PageGrain.ELPA support (diff) | |
| download | qemu-5204ea79ea739b557f47fc4db96c94edcb33a5d6.tar.gz qemu-5204ea79ea739b557f47fc4db96c94edcb33a5d6.tar.xz qemu-5204ea79ea739b557f47fc4db96c94edcb33a5d6.zip | |
target-mips: add MTHC0 and MFHC0 instructions
Implement MTHC0 and MFHC0 instructions. In MIPS32 they are used to access
upper word of extended to 64-bits CP0 registers.
In MIPS64, when CP0 destination register specified is the EntryLo0 or
EntryLo1, bits 1:0 of the GPR appear at bits 31:30 of EntryLo0 or
EntryLo1. This is to compensate for RI and XI, which were shifted to bits
63:62 by MTC0 to EntryLo0 or EntryLo1. Therefore creating separate
functions for EntryLo0 and EntryLo1.
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'linux-user/elfload.c')
0 files changed, 0 insertions, 0 deletions