diff options
| author | Petar Jovanovic | 2014-06-18 17:48:20 +0200 |
|---|---|---|
| committer | Aurelien Jarno | 2014-06-18 18:10:47 +0200 |
| commit | d279279e2b5cd40dbcc863fb66a695990f304077 (patch) | |
| tree | be2ceab016d93d2081b2546ee0c056103cbe1684 /linux-user/mips/target_cpu.h | |
| parent | bitops: provide an inline implementation of find_first_bit (diff) | |
| download | qemu-d279279e2b5cd40dbcc863fb66a695990f304077.tar.gz qemu-d279279e2b5cd40dbcc863fb66a695990f304077.tar.xz qemu-d279279e2b5cd40dbcc863fb66a695990f304077.zip | |
target-mips: implement UserLocal Register
From MIPS documentation (Volume III):
UserLocal Register (CP0 Register 4, Select 2)
Compliance Level: Recommended.
The UserLocal register is a read-write register that is not interpreted by
the hardware and conditionally readable via the RDHWR instruction.
This register only exists if the Config3-ULRI register field is set.
Privileged software may write this register with arbitrary information and
make it accessible to unprivileged software via register 29 (ULR) of the
RDHWR instruction. To do so, bit 29 of the HWREna register must be set to a
1 to enable unprivileged access to the register.
Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'linux-user/mips/target_cpu.h')
| -rw-r--r-- | linux-user/mips/target_cpu.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/linux-user/mips/target_cpu.h b/linux-user/mips/target_cpu.h index ba8e9eb1f9..19b8855000 100644 --- a/linux-user/mips/target_cpu.h +++ b/linux-user/mips/target_cpu.h @@ -30,7 +30,7 @@ static inline void cpu_clone_regs(CPUMIPSState *env, target_ulong newsp) static inline void cpu_set_tls(CPUMIPSState *env, target_ulong newtls) { - env->tls_value = newtls; + env->active_tc.CP0_UserLocal = newtls; } #endif |