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| author | Richard Henderson | 2021-10-20 05:16:57 +0200 |
|---|---|---|
| committer | Alistair Francis | 2021-10-21 23:47:51 +0200 |
| commit | e91a7227cb802ea62ffa14707ebc2f588b01213d (patch) | |
| tree | 83e6aa01014f64717ecdcf2b0b7ee2b42ef44b72 /linux-user/riscv/cpu_loop.c | |
| parent | target/riscv: Create RISCVMXL enumeration (diff) | |
| download | qemu-e91a7227cb802ea62ffa14707ebc2f588b01213d.tar.gz qemu-e91a7227cb802ea62ffa14707ebc2f588b01213d.tar.xz qemu-e91a7227cb802ea62ffa14707ebc2f588b01213d.zip | |
target/riscv: Split misa.mxl and misa.ext
The hw representation of misa.mxl is at the high bits of the
misa csr. Representing this in the same way inside QEMU
results in overly complex code trying to check that field.
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211020031709.359469-4-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'linux-user/riscv/cpu_loop.c')
| -rw-r--r-- | linux-user/riscv/cpu_loop.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c index 9859a366e4..e5bb6d908a 100644 --- a/linux-user/riscv/cpu_loop.c +++ b/linux-user/riscv/cpu_loop.c @@ -133,7 +133,7 @@ void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) env->gpr[xSP] = regs->sp; env->elf_flags = info->elf_flags; - if ((env->misa & RVE) && !(env->elf_flags & EF_RISCV_RVE)) { + if ((env->misa_ext & RVE) && !(env->elf_flags & EF_RISCV_RVE)) { error_report("Incompatible ELF: RVE cpu requires RVE ABI binary"); exit(EXIT_FAILURE); } |