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| author | Richard Henderson | 2021-09-18 15:37:19 +0200 |
|---|---|---|
| committer | Richard Henderson | 2021-11-02 12:00:52 +0100 |
| commit | 1db8af5c87ef5c89ecdb9e2d2620cd38cfbca940 (patch) | |
| tree | 5c31eb459980b5e8e08fdf32faf549b68e80496c /linux-user/riscv | |
| parent | target/openrisc: Make openrisc_cpu_tlb_fill sysemu only (diff) | |
| download | qemu-1db8af5c87ef5c89ecdb9e2d2620cd38cfbca940.tar.gz qemu-1db8af5c87ef5c89ecdb9e2d2620cd38cfbca940.tar.xz qemu-1db8af5c87ef5c89ecdb9e2d2620cd38cfbca940.zip | |
target/ppc: Implement ppc_cpu_record_sigsegv
Record DAR, DSISR, and exception_index. That last means
that we must exit to cpu_loop ourselves, instead of letting
exception_index being overwritten.
This is exactly what the user-mode ppc_cpu_tlb_fill does,
so simply rename it as ppc_cpu_record_sigsegv.
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'linux-user/riscv')
0 files changed, 0 insertions, 0 deletions