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| author | Richard Henderson | 2019-02-05 17:52:37 +0100 |
|---|---|---|
| committer | Peter Maydell | 2019-02-05 17:52:37 +0100 |
| commit | 1bafc2ba7e6bfe89fff3503fdac8db39c973de48 (patch) | |
| tree | 598335f5f41e58ee201e25ae684cc217d8ff45ec /linux-user/tilegx/signal.c | |
| parent | exec: Add target-specific tlb bits to MemTxAttrs (diff) | |
| download | qemu-1bafc2ba7e6bfe89fff3503fdac8db39c973de48.tar.gz qemu-1bafc2ba7e6bfe89fff3503fdac8db39c973de48.tar.xz qemu-1bafc2ba7e6bfe89fff3503fdac8db39c973de48.zip | |
target/arm: Cache the GP bit for a page in MemTxAttrs
Caching the bit means that we will not have to re-walk the
page tables to look up the bit during translation.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20190128223118.5255-6-richard.henderson@linaro.org
[PMM: no need to OR in guarded bit status]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'linux-user/tilegx/signal.c')
0 files changed, 0 insertions, 0 deletions