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| author | Richard Henderson | 2020-02-14 20:46:42 +0100 |
|---|---|---|
| committer | Peter Maydell | 2020-02-21 17:07:00 +0100 |
| commit | 33649de62e40df0060a1c514574e4ef25c4e52e1 (patch) | |
| tree | 2a72c0d4034ff1791740617dd1e33da064a94bce /linux-user | |
| parent | target/arm: Flush high bits of sve register after AdvSIMD TBL/TBX (diff) | |
| download | qemu-33649de62e40df0060a1c514574e4ef25c4e52e1.tar.gz qemu-33649de62e40df0060a1c514574e4ef25c4e52e1.tar.xz qemu-33649de62e40df0060a1c514574e4ef25c4e52e1.zip | |
target/arm: Flush high bits of sve register after AdvSIMD ZIP/UZP/TRN
Writes to AdvSIMD registers flush the bits above 128.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200214194643.23317-4-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'linux-user')
0 files changed, 0 insertions, 0 deletions