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| author | Alexander Graf | 2010-09-10 17:08:34 +0200 |
|---|---|---|
| committer | Edgar E. Iglesias | 2010-09-15 16:18:33 +0200 |
| commit | 41557447d30eeb944e42069513df13585f5e6c7f (patch) | |
| tree | 5c4382b8e922a57aab31d9b169b6fa3bf97b849d /linux-user | |
| parent | PPC: Enable hint bits for lwarx/ldarx (diff) | |
| download | qemu-41557447d30eeb944e42069513df13585f5e6c7f.tar.gz qemu-41557447d30eeb944e42069513df13585f5e6c7f.tar.xz qemu-41557447d30eeb944e42069513df13585f5e6c7f.zip | |
PPC: Redesign interrupt trigger path
According to the Book3S spec, the interrupt context starts with an MSR
value that is rather simple. If we leave out the HV case, it's almost
always 0.
To reflect this, let's redesign the way that MSR value gets calculated.
Using this, we also squash the bug where MSR_POW can slip through into
the interrupt handler MSR.
Reported-by: Thomas Monjalon <thomas.monjalon@openwide.fr>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Diffstat (limited to 'linux-user')
0 files changed, 0 insertions, 0 deletions