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| author | Peter Maydell | 2016-06-27 12:48:21 +0200 |
|---|---|---|
| committer | Peter Maydell | 2016-06-27 12:48:22 +0200 |
| commit | 4b86bac21c15cd04cf333423c8c256e4dc4dc925 (patch) | |
| tree | 22492178fd48b0302a06c694deb1417544454b26 /linux-user | |
| parent | Merge remote-tracking branch 'remotes/mcayland/tags/qemu-sparc-signed' into s... (diff) | |
| parent | target-mips: Add FCR31's FS bit definition (diff) | |
| download | qemu-4b86bac21c15cd04cf333423c8c256e4dc4dc925.tar.gz qemu-4b86bac21c15cd04cf333423c8c256e4dc4dc925.tar.xz qemu-4b86bac21c15cd04cf333423c8c256e4dc4dc925.zip | |
Merge remote-tracking branch 'remotes/lalrae/tags/mips-20160624' into staging
MIPS patches 2016-06-24
Changes:
* support IEEE 754-2008 in MIPS CPUs
# gpg: Signature made Fri 24 Jun 2016 16:09:38 BST
# gpg: using RSA key 0x52118E3C0B29DA6B
# gpg: Good signature from "Leon Alrae <leon.alrae@imgtec.com>"
# Primary key fingerprint: 8DD3 2F98 5495 9D66 35D4 4FC0 5211 8E3C 0B29 DA6B
* remotes/lalrae/tags/mips-20160624:
target-mips: Add FCR31's FS bit definition
target-mips: Implement FCR31's R/W bitmask and related functionalities
target-mips: Add nan2008 flavor of <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>
target-mips: Add abs2008 flavor of <ABS|NEG>.<S|D>
target-mips: Activate IEEE 754-2008 signaling NaN bit meaning for MSA
linux-user: Update preprocessor constants for Mips-specific e_flags bits
softfloat: Handle snan_bit_is_one == 0 in MIPS pickNaNMulAdd()
softfloat: For Mips only, correct default NaN values
softfloat: Clean code format in fpu/softfloat-specialize.h
softfloat: Implement run-time-configurable meaning of signaling NaN bit
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'linux-user')
| -rw-r--r-- | linux-user/main.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/linux-user/main.c b/linux-user/main.c index fd88e22fe3..78d8d04771 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -4687,6 +4687,20 @@ int main(int argc, char **argv, char **envp) if (regs->cp0_epc & 1) { env->hflags |= MIPS_HFLAG_M16; } + if (((info->elf_flags & EF_MIPS_NAN2008) != 0) != + ((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) != 0)) { + if ((env->active_fpu.fcr31_rw_bitmask & + (1 << FCR31_NAN2008)) == 0) { + fprintf(stderr, "ELF binary's NaN mode not supported by CPU\n"); + exit(1); + } + if ((info->elf_flags & EF_MIPS_NAN2008) != 0) { + env->active_fpu.fcr31 |= (1 << FCR31_NAN2008); + } else { + env->active_fpu.fcr31 &= ~(1 << FCR31_NAN2008); + } + restore_snan_bit_mode(env); + } } #elif defined(TARGET_OPENRISC) { |