diff options
| author | Richard Henderson | 2020-08-20 07:37:40 +0200 |
|---|---|---|
| committer | Richard Henderson | 2020-09-01 16:41:38 +0200 |
| commit | 6efd55995a224787baa712500b82ef21a148d38e (patch) | |
| tree | 6d34b48064a7c5b6527062ac2725ca4185a34713 /linux-user | |
| parent | target/microblaze: Fix width of MSR (diff) | |
| download | qemu-6efd55995a224787baa712500b82ef21a148d38e.tar.gz qemu-6efd55995a224787baa712500b82ef21a148d38e.tar.xz qemu-6efd55995a224787baa712500b82ef21a148d38e.zip | |
target/microblaze: Fix width of ESR
The exception status register is only 32-bits wide.
Do not use a 64-bit type to represent it.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'linux-user')
| -rw-r--r-- | linux-user/microblaze/cpu_loop.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/linux-user/microblaze/cpu_loop.c b/linux-user/microblaze/cpu_loop.c index da5e98b784..3de99ea311 100644 --- a/linux-user/microblaze/cpu_loop.c +++ b/linux-user/microblaze/cpu_loop.c @@ -106,7 +106,7 @@ void cpu_loop(CPUMBState *env) queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; default: - fprintf(stderr, "Unhandled hw-exception: 0x%" PRIx64 "\n", + fprintf(stderr, "Unhandled hw-exception: 0x%x\n", env->esr & ESR_EC_MASK); cpu_dump_state(cs, stderr, 0); exit(EXIT_FAILURE); |