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| author | Xiaoyao Li | 2019-12-25 07:30:17 +0100 |
|---|---|---|
| committer | Paolo Bonzini | 2020-01-07 14:30:53 +0100 |
| commit | 6c997b4adb300788d61d72e2b8bc67c03a584956 (patch) | |
| tree | 49aeb158eff60bc339784588b15242dde5ae1923 /memory_ldst.inc.c | |
| parent | target/i386: Fix handling of k_gs_base register in 32-bit mode in gdbstub (diff) | |
| download | qemu-6c997b4adb300788d61d72e2b8bc67c03a584956.tar.gz qemu-6c997b4adb300788d61d72e2b8bc67c03a584956.tar.xz qemu-6c997b4adb300788d61d72e2b8bc67c03a584956.zip | |
target/i386: Add new bit definitions of MSR_IA32_ARCH_CAPABILITIES
The bit 6, 7 and 8 of MSR_IA32_ARCH_CAPABILITIES are recently disclosed
for some security issues. Add the definitions for them to be used by named
CPU models.
Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
Message-Id: <20191225063018.20038-2-xiaoyao.li@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'memory_ldst.inc.c')
0 files changed, 0 insertions, 0 deletions