diff options
author | bellard | 2006-03-25 02:25:02 +0100 |
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committer | bellard | 2006-03-25 02:25:02 +0100 |
commit | 26f69dc09fa3c459fca53bbfd267cbfc2682201e (patch) | |
tree | a20a7b57c7b526fc66673f4bde41938ae05053aa /pc-bios/vgabios.diff | |
parent | Rename --*able-softmmu --*able-system. (diff) | |
download | qemu-26f69dc09fa3c459fca53bbfd267cbfc2682201e.tar.gz qemu-26f69dc09fa3c459fca53bbfd267cbfc2682201e.tar.xz qemu-26f69dc09fa3c459fca53bbfd267cbfc2682201e.zip |
upgrade to latest vgabios version - added Video Parameter Table support - added 1600x1200x8 Cirrus mode
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1789 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'pc-bios/vgabios.diff')
-rw-r--r-- | pc-bios/vgabios.diff | 864 |
1 files changed, 789 insertions, 75 deletions
diff --git a/pc-bios/vgabios.diff b/pc-bios/vgabios.diff index d3a3ef7a2a..73159a0fd0 100644 --- a/pc-bios/vgabios.diff +++ b/pc-bios/vgabios.diff @@ -1,97 +1,811 @@ -? biossums -? vgabios.cirrus.debug.txt -? vgabios.cirrus.txt -? vgabios.debug.txt -? vgabios.txt -? tests/Makefile -? tests/setmode.S -? tests/setmode.c -? tests/setmode.com -? tests/setmode.elf Index: Makefile =================================================================== -RCS file: /cvsroot/vgabios/vgabios/Makefile,v -retrieving revision 1.15 -diff -u -w -r1.15 Makefile -Index: VGABIOS-lgpl-latest.bin -=================================================================== -RCS file: /cvsroot/vgabios/vgabios/VGABIOS-lgpl-latest.bin,v -retrieving revision 1.60 -diff -u -w -r1.60 VGABIOS-lgpl-latest.bin -Binary files /tmp/cvsCahrMA and VGABIOS-lgpl-latest.bin differ -Index: VGABIOS-lgpl-latest.cirrus.bin -=================================================================== -RCS file: /cvsroot/vgabios/vgabios/VGABIOS-lgpl-latest.cirrus.bin,v -retrieving revision 1.12 -diff -u -w -r1.12 VGABIOS-lgpl-latest.cirrus.bin -Binary files /tmp/cvsewygNU and VGABIOS-lgpl-latest.cirrus.bin differ -Index: VGABIOS-lgpl-latest.cirrus.debug.bin -=================================================================== -RCS file: /cvsroot/vgabios/vgabios/VGABIOS-lgpl-latest.cirrus.debug.bin,v -retrieving revision 1.12 -diff -u -w -r1.12 VGABIOS-lgpl-latest.cirrus.debug.bin -Binary files /tmp/cvsey9TQf and VGABIOS-lgpl-latest.cirrus.debug.bin differ -Index: VGABIOS-lgpl-latest.debug.bin -=================================================================== -RCS file: /cvsroot/vgabios/vgabios/VGABIOS-lgpl-latest.debug.bin,v -retrieving revision 1.60 -diff -u -w -r1.60 VGABIOS-lgpl-latest.debug.bin -Binary files /tmp/cvskxbTbC and VGABIOS-lgpl-latest.debug.bin differ +RCS file: /sources/vgabios/vgabios/Makefile,v +retrieving revision 1.17 +diff -u -w -r1.17 Makefile +--- Makefile 6 Mar 2005 13:06:47 -0000 1.17 ++++ Makefile 25 Mar 2006 01:19:02 -0000 +@@ -17,9 +17,9 @@ + all: bios cirrus-bios + + +-bios: biossums vgabios.bin vgabios.debug.bin ++bios: biossums vgabios.bin #vgabios.debug.bin + +-cirrus-bios: vgabios-cirrus.bin vgabios-cirrus.debug.bin ++cirrus-bios: vgabios-cirrus.bin #vgabios-cirrus.debug.bin + + clean: + /bin/rm -f biossums *.o *.s *.ld86 \ Index: clext.c =================================================================== -RCS file: /cvsroot/vgabios/vgabios/clext.c,v -retrieving revision 1.8 -diff -u -w -r1.8 clext.c ---- clext.c 8 Aug 2004 16:52:55 -0000 1.8 -+++ clext.c 30 Nov 2004 23:38:32 -0000 -@@ -222,7 +222,21 @@ - 0x001a,0x221b,0x001d, +RCS file: /sources/vgabios/vgabios/clext.c,v +retrieving revision 1.9 +diff -u -w -r1.9 clext.c +--- clext.c 4 Dec 2004 15:26:17 -0000 1.9 ++++ clext.c 25 Mar 2006 01:19:03 -0000 +@@ -238,6 +238,21 @@ 0xffff }; -- -+/* 1280x1024x16 */ -+unsigned short cseq_1280x1024x16[] = { -+0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707, + ++/* 1600x1200x8 */ ++unsigned short cseq_1600x1200x8[] = { ++0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107, +0x760b,0x760c,0x760d,0x760e, +0x0412,0x0013,0x2017, +0x341b,0x341c,0x341d,0x341e, +0xffff +}; -+unsigned short ccrtc_1280x1024x16[] = { ++unsigned short ccrtc_1600x1200x8[] = { +0x2911,0xc300,0x9f01,0x9f02,0x8603,0x8304,0x9405,0x2406,0xf707, +0x6009,0x000c,0x000d, -+0x0310,0xff12,0x4013,0x4014,0xff15,0x2416,0xc317,0xff18, -+0x001a,0x321b,0x001d, ++0x0310,0xff12,0xa013,0x4014,0xff15,0x2416,0xc317,0xff18, ++0x001a,0x221b,0x001d, +0xffff +}; cirrus_mode_t cirrus_modes[] = { -@@ -269,6 +283,12 @@ - {0x6d,1280,1024,8,0x00, - cseq_1280x1024x8,cgraph_svgacolor,ccrtc_1280x1024x8,8, - 4,0,0,0,0,0,0,0,0}, -+ {0x69,1280,1024,15,0xf0, -+ cseq_1280x1024x16,cgraph_svgacolor,ccrtc_1280x1024x16,16, -+ 6,5,10,5,5,5,0,1,15}, -+ {0x75,1280,1024,16,0xe1, -+ cseq_1280x1024x16,cgraph_svgacolor,ccrtc_1280x1024x16,16, -+ 6,5,11,6,5,5,0,0,0}, +@@ -291,6 +306,10 @@ + cseq_1280x1024x16,cgraph_svgacolor,ccrtc_1280x1024x16,16, + 6,5,11,6,5,5,0,0,0}, ++ {0x7b,1600,1200,8,0x00, ++ cseq_1600x1200x8,cgraph_svgacolor,ccrtc_1600x1200x8,8, ++ 4,0,0,0,0,0,0,0,0}, ++ {0xfe,0,0,0,0,cseq_vga,cgraph_vga,ccrtc_vga,0, 0xff,0,0,0,0,0,0,0,0}, -@@ -310,9 +330,13 @@ - // 1024x768x16 - 0x117, 0x74, - // 1024x768x24 --//0x118, 0x79, -+ 0x118, 0x79, - // 1280x1024x8 - 0x107, 0x6d, -+// 1280x1024x15 -+ 0x119, 0x69, -+// 1280x1024x16 -+ 0x11a, 0x75, - // invalid - 0xffff,0xffff + {0xff,0,0,0,0,0,0,0,0, +Index: vgabios.c +=================================================================== +RCS file: /sources/vgabios/vgabios/vgabios.c,v +retrieving revision 1.63 +diff -u -w -r1.63 vgabios.c +--- vgabios.c 26 Dec 2005 19:50:26 -0000 1.63 ++++ vgabios.c 25 Mar 2006 01:19:03 -0000 +@@ -111,6 +111,7 @@ + static void biosfn_read_video_state_size(); + static void biosfn_save_video_state(); + static void biosfn_restore_video_state(); ++extern Bit8u video_save_pointer_table[]; + + // This is for compiling with gcc2 and gcc3 + #define ASM_START #asm +@@ -459,6 +460,29 @@ + + pop ds + ret ++ ++_video_save_pointer_table: ++ .word _video_param_table ++ .word 0xc000 ++ ++ .word 0 /* XXX: fill it */ ++ .word 0 ++ ++ .word 0 /* XXX: fill it */ ++ .word 0 ++ ++ .word 0 /* XXX: fill it */ ++ .word 0 ++ ++ .word 0 /* XXX: fill it */ ++ .word 0 ++ ++ .word 0 /* XXX: fill it */ ++ .word 0 ++ ++ .word 0 /* XXX: fill it */ ++ .word 0 ++ + ASM_END + + // -------------------------------------------------------------------------------------------- +@@ -780,8 +804,8 @@ + + // Should we clear the screen ? + Bit8u noclearmem=mode&0x80; +- Bit8u line,mmask,*palette; +- Bit16u i,twidth,theight,cheight; ++ Bit8u line,mmask,*palette,vpti; ++ Bit16u i,twidth,theightm1,cheight; + Bit8u modeset_ctl,video_ctl,vga_switches; + Bit16u crtc_addr; + +@@ -804,9 +828,10 @@ + if(line==0xFF) + return; + +- twidth=vga_modes[line].twidth; +- theight=vga_modes[line].theight; +- cheight=vga_modes[line].cheight; ++ vpti=line_to_vpti[line]; ++ twidth=video_param_table[vpti].twidth; ++ theightm1=video_param_table[vpti].theightm1; ++ cheight=video_param_table[vpti].cheight; + + // Read the bios vga control + video_ctl=read_byte(BIOSMEM_SEG,BIOSMEM_VIDEO_CTL); +@@ -866,21 +891,25 @@ + inb(VGAREG_ACTL_RESET); + + // Set Attribute Ctl +- for(i=0;i<=ACTL_MAX_REG;i++) ++ for(i=0;i<=0x13;i++) + {outb(VGAREG_ACTL_ADDRESS,i); +- outb(VGAREG_ACTL_WRITE_DATA,actl_regs[vga_modes[line].actlmodel][i]); ++ outb(VGAREG_ACTL_WRITE_DATA,video_param_table[vpti].actl_regs[i]); + } ++ outb(VGAREG_ACTL_ADDRESS,0x14); ++ outb(VGAREG_ACTL_WRITE_DATA,0x00); + + // Set Sequencer Ctl +- for(i=0;i<=SEQU_MAX_REG;i++) ++ outb(VGAREG_SEQU_ADDRESS,0); ++ outb(VGAREG_SEQU_DATA,0x03); ++ for(i=1;i<=4;i++) + {outb(VGAREG_SEQU_ADDRESS,i); +- outb(VGAREG_SEQU_DATA,sequ_regs[vga_modes[line].sequmodel][i]); ++ outb(VGAREG_SEQU_DATA,video_param_table[vpti].sequ_regs[i - 1]); + } + + // Set Grafx Ctl +- for(i=0;i<=GRDC_MAX_REG;i++) ++ for(i=0;i<=8;i++) + {outb(VGAREG_GRDC_ADDRESS,i); +- outb(VGAREG_GRDC_DATA,grdc_regs[vga_modes[line].grdcmodel][i]); ++ outb(VGAREG_GRDC_DATA,video_param_table[vpti].grdc_regs[i]); + } + + // Set CRTC address VGA or MDA +@@ -889,13 +918,13 @@ + // Disable CRTC write protection + outw(crtc_addr,0x0011); + // Set CRTC regs +- for(i=0;i<=CRTC_MAX_REG;i++) ++ for(i=0;i<=0x18;i++) + {outb(crtc_addr,i); +- outb(crtc_addr+1,crtc_regs[vga_modes[line].crtcmodel][i]); ++ outb(crtc_addr+1,video_param_table[vpti].crtc_regs[i]); + } + + // Set the misc register +- outb(VGAREG_WRITE_MISC_OUTPUT,vga_modes[line].miscreg); ++ outb(VGAREG_WRITE_MISC_OUTPUT,video_param_table[vpti].miscreg); + + // Enable video + outb(VGAREG_ACTL_ADDRESS,0x20); +@@ -927,9 +956,9 @@ + // Set the BIOS mem + write_byte(BIOSMEM_SEG,BIOSMEM_CURRENT_MODE,mode); + write_word(BIOSMEM_SEG,BIOSMEM_NB_COLS,twidth); +- write_word(BIOSMEM_SEG,BIOSMEM_PAGE_SIZE,vga_modes[line].slength); ++ write_word(BIOSMEM_SEG,BIOSMEM_PAGE_SIZE,*(Bit16u *)&video_param_table[vpti].slength_l); + write_word(BIOSMEM_SEG,BIOSMEM_CRTC_ADDRESS,crtc_addr); +- write_byte(BIOSMEM_SEG,BIOSMEM_NB_ROWS,theight-1); ++ write_byte(BIOSMEM_SEG,BIOSMEM_NB_ROWS,theightm1); + write_word(BIOSMEM_SEG,BIOSMEM_CHAR_HEIGHT,cheight); + write_byte(BIOSMEM_SEG,BIOSMEM_VIDEO_CTL,(0x60|noclearmem)); + write_byte(BIOSMEM_SEG,BIOSMEM_SWITCHES,0xF9); +@@ -937,8 +966,8 @@ + + // FIXME We nearly have the good tables. to be reworked + write_byte(BIOSMEM_SEG,BIOSMEM_DCC_INDEX,0x08); // 8 is VGA should be ok for now +- write_word(BIOSMEM_SEG,BIOSMEM_VS_POINTER,0x00); +- write_word(BIOSMEM_SEG,BIOSMEM_VS_POINTER+2,0x00); ++ write_word(BIOSMEM_SEG,BIOSMEM_VS_POINTER, video_save_pointer_table); ++ write_word(BIOSMEM_SEG,BIOSMEM_VS_POINTER+2, 0xc000); + + // FIXME + write_byte(BIOSMEM_SEG,BIOSMEM_CURRENT_MSR,0x00); // Unavailable on vanilla vga, but... +@@ -1114,7 +1143,7 @@ + } + else + { +- address = page*vga_modes[line].slength; ++ address = page * (*(Bit16u *)&video_param_table[line_to_vpti[line]].slength_l); + } + + // CRTC regs 0x0c and 0x0d +@@ -1271,7 +1300,7 @@ + else + { + // FIXME gfx mode not complete +- cheight=vga_modes[line].cheight; ++ cheight=video_param_table[line_to_vpti[line]].cheight; + switch(vga_modes[line].memmodel) + { + case PLANAR4: +@@ -1581,7 +1610,7 @@ + else + { + // FIXME gfx mode not complete +- cheight=vga_modes[line].cheight; ++ cheight=video_param_table[line_to_vpti[line]].cheight; + bpp=vga_modes[line].pixbits; + while((count-->0) && (xcurs<nbcols)) + { +@@ -1641,7 +1670,7 @@ + else + { + // FIXME gfx mode not complete +- cheight=vga_modes[line].cheight; ++ cheight=video_param_table[line_to_vpti[line]].cheight; + bpp=vga_modes[line].pixbits; + while((count-->0) && (xcurs<nbcols)) + { +@@ -1949,7 +1978,7 @@ + else + { + // FIXME gfx mode not complete +- cheight=vga_modes[line].cheight; ++ cheight=video_param_table[line_to_vpti[line]].cheight; + bpp=vga_modes[line].pixbits; + switch(vga_modes[line].memmodel) + { +Index: vgatables.h +=================================================================== +RCS file: /sources/vgabios/vgabios/vgatables.h,v +retrieving revision 1.9 +diff -u -w -r1.9 vgatables.h +--- vgatables.h 21 Sep 2005 18:45:20 -0000 1.9 ++++ vgatables.h 25 Mar 2006 01:19:04 -0000 +@@ -77,7 +77,7 @@ + * Tables of default values for each mode + * + */ +-#define MODE_MAX 0x14 ++#define MODE_MAX 15 + #define TEXT 0x00 + #define GRAPH 0x01 + +@@ -96,126 +96,38 @@ + + typedef struct + {Bit8u svgamode; +- Bit16u vesamode; + Bit8u class; /* TEXT, GRAPH */ + Bit8u memmodel; /* CTEXT,MTEXT,CGA,PL1,PL2,PL4,P8,P15,P16,P24,P32 */ +- Bit8u nbpages; + Bit8u pixbits; +- Bit16u swidth, sheight; +- Bit16u twidth, theight; +- Bit16u cwidth, cheight; + Bit16u sstart; +- Bit16u slength; +- Bit8u miscreg; + Bit8u pelmask; +- Bit8u crtcmodel; +- Bit8u actlmodel; +- Bit8u grdcmodel; +- Bit8u sequmodel; + Bit8u dacmodel; /* 0 1 2 3 */ + } VGAMODES; + + static VGAMODES vga_modes[MODE_MAX+1]= +-{//mode vesa class model pg bits sw sh tw th cw ch sstart slength misc pelm crtc actl gdc sequ dac +- {0x00, 0xFFFF, TEXT, CTEXT, 8, 4, 360, 400, 40, 25, 9, 16, 0xB800, 0x0800, 0x67, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x02}, +- {0x01, 0xFFFF, TEXT, CTEXT, 8, 4, 360, 400, 40, 25, 9, 16, 0xB800, 0x0800, 0x67, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x02}, +- {0x02, 0xFFFF, TEXT, CTEXT, 4, 4, 720, 400, 80, 25, 9, 16, 0xB800, 0x1000, 0x67, 0xFF, 0x01, 0x00, 0x00, 0x01, 0x02}, +- {0x03, 0xFFFF, TEXT, CTEXT, 4, 4, 720, 400, 80, 25, 9, 16, 0xB800, 0x1000, 0x67, 0xFF, 0x01, 0x00, 0x00, 0x01, 0x02}, +- {0x04, 0xFFFF, GRAPH, CGA, 4, 2, 320, 200, 40, 25, 8, 8, 0xB800, 0x0800, 0x63, 0xFF, 0x02, 0x01, 0x01, 0x02, 0x01}, +- {0x05, 0xFFFF, GRAPH, CGA, 1, 2, 320, 200, 40, 25, 8, 8, 0xB800, 0x0800, 0x63, 0xFF, 0x02, 0x01, 0x01, 0x02, 0x01}, +- {0x06, 0xFFFF, GRAPH, CGA, 1, 1, 640, 200, 80, 25, 8, 8, 0xB800, 0x1000, 0x63, 0xFF, 0x03, 0x02, 0x02, 0x03, 0x01}, +- {0x07, 0xFFFF, TEXT, MTEXT, 4, 4, 720, 400, 80, 25, 9, 16, 0xB000, 0x1000, 0x66, 0xFF, 0x04, 0x03, 0x03, 0x01, 0x00}, +- {0x0D, 0xFFFF, GRAPH, PLANAR4, 8, 4, 320, 200, 40, 25, 8, 8, 0xA000, 0x2000, 0x63, 0xFF, 0x05, 0x04, 0x04, 0x04, 0x01}, +- {0x0E, 0xFFFF, GRAPH, PLANAR4, 4, 4, 640, 200, 80, 25, 8, 8, 0xA000, 0x4000, 0x63, 0xFF, 0x06, 0x04, 0x04, 0x05, 0x01}, +- {0x0F, 0xFFFF, GRAPH, PLANAR1, 2, 1, 640, 350, 80, 25, 8, 14, 0xA000, 0x8000, 0xa3, 0xFF, 0x07, 0x05, 0x04, 0x05, 0x00}, +- {0x10, 0xFFFF, GRAPH, PLANAR4, 2, 4, 640, 350, 80, 25, 8, 14, 0xA000, 0x8000, 0xa3, 0xFF, 0x07, 0x06, 0x04, 0x05, 0x02}, +- {0x11, 0xFFFF, GRAPH, PLANAR1, 1, 1, 640, 480, 80, 30, 8, 16, 0xA000, 0x0000, 0xe3, 0xFF, 0x08, 0x07, 0x04, 0x05, 0x02}, +- {0x12, 0xFFFF, GRAPH, PLANAR4, 1, 4, 640, 480, 80, 30, 8, 16, 0xA000, 0x0000, 0xe3, 0xFF, 0x08, 0x06, 0x04, 0x05, 0x02}, +- {0x13, 0xFFFF, GRAPH, LINEAR8, 1, 8, 320, 200, 40, 25, 8, 8, 0xA000, 0x0000, 0x63, 0xFF, 0x09, 0x08, 0x05, 0x06, 0x03}, +- {0x6A, 0xFFFF, GRAPH, PLANAR4, 1, 4, 800, 600,100, 37, 8, 16, 0xA000, 0x0000, 0xe3, 0xFF, 0x0A, 0x06, 0x04, 0x05, 0x02} +-}; +- +-/* CRTC */ +-#define CRTC_MAX_REG 0x18 +-#define CRTC_MAX_MODEL 0x0A +-static Bit8u crtc_access[CRTC_MAX_REG+1]= +-{ /* 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 */ +- 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 +-}; +-static Bit8u crtc_regs[CRTC_MAX_MODEL+1][CRTC_MAX_REG+1]= +-{/* Model 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 */ +- /* 00 */ 0x2d,0x27,0x28,0x90,0x2b,0xa0,0xbf,0x1f,0x00,0x4f,0x0d,0x0e,0x00,0x00,0x00,0x00,0x9c,0x8e,0x8f,0x14,0x1f,0x96,0xb9,0xa3,0xff, +- /* 01 */ 0x5f,0x4f,0x50,0x82,0x55,0x81,0xbf,0x1f,0x00,0x4f,0x0d,0x0e,0x00,0x00,0x00,0x00,0x9c,0x8e,0x8f,0x28,0x1f,0x96,0xb9,0xa3,0xff, +- /* 02 */ 0x2d,0x27,0x28,0x90,0x2b,0x80,0xbf,0x1f,0x00,0xc1,0x00,0x00,0x00,0x00,0x00,0x00,0x9c,0x8e,0x8f,0x14,0x00,0x96,0xb9,0xa2,0xff, +- /* 03 */ 0x5f,0x4f,0x50,0x82,0x54,0x80,0xbf,0x1f,0x00,0xc1,0x00,0x00,0x00,0x00,0x00,0x00,0x9c,0x8e,0x8f,0x28,0x00,0x96,0xb9,0xc2,0xff, +- /* 04 */ 0x5f,0x4f,0x50,0x82,0x55,0x81,0xbf,0x1f,0x00,0x4f,0x0d,0x0e,0x00,0x00,0x00,0x00,0x9c,0x8e,0x8f,0x28,0x0f,0x96,0xb9,0xa3,0xff, +- /* 05 */ 0x2d,0x27,0x28,0x90,0x2b,0x80,0xbf,0x1f,0x00,0xc0,0x00,0x00,0x00,0x00,0x00,0x00,0x9c,0x8e,0x8f,0x14,0x00,0x96,0xb9,0xe3,0xff, +- /* 06 */ 0x5f,0x4f,0x50,0x82,0x54,0x80,0xbf,0x1f,0x00,0xc0,0x00,0x00,0x00,0x00,0x00,0x00,0x9c,0x8e,0x8f,0x28,0x00,0x96,0xb9,0xe3,0xff, +- /* 07 */ 0x5f,0x4f,0x50,0x82,0x54,0x80,0xbf,0x1f,0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x83,0x85,0x5d,0x28,0x0f,0x63,0xba,0xe3,0xff, +- /* 08 */ 0x5f,0x4f,0x50,0x82,0x54,0x80,0x0b,0x3e,0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0xea,0x8c,0xdf,0x28,0x00,0xe7,0x04,0xe3,0xff, +- /* 09 */ 0x5f,0x4f,0x50,0x82,0x54,0x80,0xbf,0x1f,0x00,0x41,0x00,0x00,0x00,0x00,0x00,0x00,0x9c,0x8e,0x8f,0x28,0x40,0x96,0xb9,0xa3,0xff, +- /* 0A */ 0x7f,0x63,0x63,0x83,0x6b,0x1b,0x72,0xf0,0x00,0x60,0x00,0x00,0x00,0x00,0x00,0x00,0x59,0x8d,0x57,0x32,0x00,0x57,0x73,0xe3,0xff +-}; +- +-/* Attribute Controler 0x3c0 */ +-#define ACTL_MAX_REG 0x14 +-#define ACTL_MAX_MODEL 0x08 +- +-static Bit8u actl_access[ACTL_MAX_REG+1]= +-{/* 00 01 02 03 04 05 06 07 08 09 0A 0B OC OD OE OF 10 11 12 13 14 */ +- 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 +-}; +- +-static Bit8u actl_regs[ACTL_MAX_MODEL+1][ACTL_MAX_REG+1]= +-{/* Model 00 01 02 03 04 05 06 07 08 09 0A 0B OC OD OE OF 10 11 12 13 14 */ +- /* 00 */ 0x00,0x01,0x02,0x03,0x04,0x05,0x14,0x07,0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f,0x0c,0x00,0x0f,0x08,0x00, +- /* 01 */ 0x00,0x13,0x15,0x17,0x02,0x04,0x06,0x07,0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x01,0x00,0x03,0x00,0x00, +- /* 02 */ 0x00,0x17,0x17,0x17,0x17,0x17,0x17,0x17,0x17,0x17,0x17,0x17,0x17,0x17,0x17,0x17,0x01,0x00,0x01,0x00,0x00, +- /* 03 */ 0x00,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x10,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x0e,0x00,0x0f,0x08,0x00, +- /* 04 */ 0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x01,0x00,0x0f,0x00,0x00, +- /* 05 */ 0x00,0x08,0x00,0x00,0x18,0x18,0x00,0x00,0x00,0x08,0x00,0x00,0x00,0x18,0x00,0x00,0x01,0x00,0x01,0x00,0x00, +- /* 06 */ 0x00,0x01,0x02,0x03,0x04,0x05,0x14,0x07,0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f,0x01,0x00,0x0f,0x00,0x00, +- /* 07 */ 0x00,0x3f,0x00,0x3f,0x00,0x3f,0x00,0x3f,0x00,0x3f,0x00,0x3f,0x00,0x3f,0x00,0x3f,0x01,0x00,0x0f,0x00,0x00, +- /* 08 */ 0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x41,0x00,0x0f,0x00,0x00 +-}; +- +-/* Sequencer 0x3c4 */ +-#define SEQU_MAX_REG 0x04 +-#define SEQU_MAX_MODEL 0x06 +- +-static Bit8u sequ_access[SEQU_MAX_REG+1]= +-{ /* 00 01 02 03 04 */ +- 0x00,0x00,0x00,0x00,0x00 +-}; +- +-static Bit8u sequ_regs[SEQU_MAX_MODEL+1][SEQU_MAX_REG+1]= +-{/* Model 00 01 02 03 04 */ +- /* 00 */ 0x03,0x08,0x03,0x00,0x02, +- /* 01 */ 0x03,0x00,0x03,0x00,0x02, +- /* 02 */ 0x03,0x09,0x03,0x00,0x02, +- /* 03 */ 0x03,0x01,0x01,0x00,0x06, +- /* 04 */ 0x03,0x09,0x0f,0x00,0x06, +- /* 05 */ 0x03,0x01,0x0f,0x00,0x06, +- /* 06 */ 0x03,0x01,0x0f,0x00,0x0e +-}; +- +-/* Graphic ctl 0x3ce */ +-#define GRDC_MAX_REG 0x08 +-#define GRDC_MAX_MODEL 0x05 +- +-static Bit8u grdc_access[GRDC_MAX_REG+1]= +-{ /* 00 01 02 03 04 05 06 07 08 */ +- 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 +-}; +- +-static Bit8u grdc_regs[GRDC_MAX_MODEL+1][GRDC_MAX_REG+1]= +-{/* Model 00 01 02 03 04 05 06 07 08 */ +- /* 00 */ 0x00,0x00,0x00,0x00,0x00,0x10,0x0e,0x0f,0xff, +- /* 01 */ 0x00,0x00,0x00,0x00,0x00,0x30,0x0f,0x0f,0xff, +- /* 02 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x0d,0x0f,0xff, +- /* 03 */ 0x00,0x00,0x00,0x00,0x00,0x10,0x0a,0x0f,0xff, +- /* 04 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0f,0xff, +- /* 05 */ 0x00,0x00,0x00,0x00,0x00,0x40,0x05,0x0f,0xff ++{//mode class model bits sstart pelm dac ++ {0x00, TEXT, CTEXT, 4, 0xB800, 0xFF, 0x02}, ++ {0x01, TEXT, CTEXT, 4, 0xB800, 0xFF, 0x02}, ++ {0x02, TEXT, CTEXT, 4, 0xB800, 0xFF, 0x02}, ++ {0x03, TEXT, CTEXT, 4, 0xB800, 0xFF, 0x02}, ++ {0x04, GRAPH, CGA, 2, 0xB800, 0xFF, 0x01}, ++ {0x05, GRAPH, CGA, 2, 0xB800, 0xFF, 0x01}, ++ {0x06, GRAPH, CGA, 1, 0xB800, 0xFF, 0x01}, ++ {0x07, TEXT, MTEXT, 4, 0xB000, 0xFF, 0x00}, ++ {0x0D, GRAPH, PLANAR4, 4, 0xA000, 0xFF, 0x01}, ++ {0x0E, GRAPH, PLANAR4, 4, 0xA000, 0xFF, 0x01}, ++ {0x0F, GRAPH, PLANAR1, 1, 0xA000, 0xFF, 0x00}, ++ {0x10, GRAPH, PLANAR4, 4, 0xA000, 0xFF, 0x02}, ++ {0x11, GRAPH, PLANAR1, 1, 0xA000, 0xFF, 0x02}, ++ {0x12, GRAPH, PLANAR4, 4, 0xA000, 0xFF, 0x02}, ++ {0x13, GRAPH, LINEAR8, 8, 0xA000, 0xFF, 0x03}, ++ {0x6A, GRAPH, PLANAR4, 4, 0xA000, 0xFF, 0x02} ++}; ++ ++/* convert index in vga_modes[] to index in video_param_table[] */ ++static Bit8u line_to_vpti[MODE_MAX+1]={ ++ 0x17, 0x17, 0x18, 0x18, 0x04, 0x05, 0x06, 0x07, ++ 0x0d, 0x0e, 0x11, 0x12, 0x1a, 0x1b, 0x1c, 0x1d, }; + + /* Default Palette */ +@@ -224,6 +136,398 @@ + static Bit8u dac_regs[DAC_MAX_MODEL+1]= + {0x3f,0x3f,0x3f,0xff}; + ++/* standard BIOS Video Parameter Table */ ++typedef struct { ++ Bit8u twidth; ++ Bit8u theightm1; ++ Bit8u cheight; ++ Bit8u slength_l; ++ Bit8u slength_h; ++ Bit8u sequ_regs[4]; ++ Bit8u miscreg; ++ Bit8u crtc_regs[25]; ++ Bit8u actl_regs[20]; ++ Bit8u grdc_regs[9]; ++} VideoParamTableEntry; ++ ++static VideoParamTableEntry video_param_table[30] = { ++{ ++ /* index=0x00 no mode defined */ ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++}, ++{ ++ /* index=0x01 no mode defined */ ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++}, ++{ ++ /* index=0x02 no mode defined */ ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++}, ++{ ++ /* index=0x03 no mode defined */ ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++}, ++{ ++ /* index=0x04 vga mode 0x04 */ ++ 40, 24, 8, 0x00, 0x08, /* tw, th-1, ch, slength */ ++ 0x09, 0x03, 0x00, 0x02, /* sequ_regs */ ++ 0x63, /* miscreg */ ++ 0x2d, 0x27, 0x28, 0x90, 0x2b, 0x80, 0xbf, 0x1f, ++ 0x00, 0xc1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x9c, 0x8e, 0x8f, 0x14, 0x00, 0x96, 0xb9, 0xa2, ++ 0xff, /* crtc_regs */ ++ 0x00, 0x13, 0x15, 0x17, 0x02, 0x04, 0x06, 0x07, ++ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, ++ 0x01, 0x00, 0x03, 0x00, /* actl_regs */ ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0f, 0x0f, 0xff, /* grdc_regs */ ++}, ++{ ++ /* index=0x05 vga mode 0x05 */ ++ 40, 24, 8, 0x00, 0x08, /* tw, th-1, ch, slength */ ++ 0x09, 0x03, 0x00, 0x02, /* sequ_regs */ ++ 0x63, /* miscreg */ ++ 0x2d, 0x27, 0x28, 0x90, 0x2b, 0x80, 0xbf, 0x1f, ++ 0x00, 0xc1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x9c, 0x8e, 0x8f, 0x14, 0x00, 0x96, 0xb9, 0xa2, ++ 0xff, /* crtc_regs */ ++ 0x00, 0x13, 0x15, 0x17, 0x02, 0x04, 0x06, 0x07, ++ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, ++ 0x01, 0x00, 0x03, 0x00, /* actl_regs */ ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0f, 0x0f, 0xff, /* grdc_regs */ ++}, ++{ ++ /* index=0x06 vga mode 0x06 */ ++ 80, 24, 8, 0x00, 0x10, /* tw, th-1, ch, slength */ ++ 0x01, 0x01, 0x00, 0x06, /* sequ_regs */ ++ 0x63, /* miscreg */ ++ 0x5f, 0x4f, 0x50, 0x82, 0x54, 0x80, 0xbf, 0x1f, ++ 0x00, 0xc1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x9c, 0x8e, 0x8f, 0x28, 0x00, 0x96, 0xb9, 0xc2, ++ 0xff, /* crtc_regs */ ++ 0x00, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17, ++ 0x17, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17, ++ 0x01, 0x00, 0x01, 0x00, /* actl_regs */ ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0d, 0x0f, 0xff, /* grdc_regs */ ++}, ++{ ++ /* index=0x07 vga mode 0x07 */ ++ 80, 24, 16, 0x00, 0x10, /* tw, th-1, ch, slength */ ++ 0x00, 0x03, 0x00, 0x02, /* sequ_regs */ ++ 0x66, /* miscreg */ ++ 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, ++ 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, ++ 0x9c, 0x8e, 0x8f, 0x28, 0x0f, 0x96, 0xb9, 0xa3, ++ 0xff, /* crtc_regs */ ++ 0x00, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, ++ 0x10, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, ++ 0x0e, 0x00, 0x0f, 0x08, /* actl_regs */ ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x0a, 0x0f, 0xff, /* grdc_regs */ ++}, ++{ ++ /* index=0x08 no mode defined */ ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++}, ++{ ++ /* index=0x09 no mode defined */ ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++}, ++{ ++ /* index=0x0a no mode defined */ ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++}, ++{ ++ /* index=0x0b no mode defined */ ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++}, ++{ ++ /* index=0x0c no mode defined */ ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++}, ++{ ++ /* index=0x0d vga mode 0x0d */ ++ 40, 24, 8, 0x00, 0x20, /* tw, th-1, ch, slength */ ++ 0x09, 0x0f, 0x00, 0x06, /* sequ_regs */ ++ 0x63, /* miscreg */ ++ 0x2d, 0x27, 0x28, 0x90, 0x2b, 0x80, 0xbf, 0x1f, ++ 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x9c, 0x8e, 0x8f, 0x14, 0x00, 0x96, 0xb9, 0xe3, ++ 0xff, /* crtc_regs */ ++ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, ++ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, ++ 0x01, 0x00, 0x0f, 0x00, /* actl_regs */ ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, 0xff, /* grdc_regs */ ++}, ++{ ++ /* index=0x0e vga mode 0x0e */ ++ 80, 24, 8, 0x00, 0x40, /* tw, th-1, ch, slength */ ++ 0x01, 0x0f, 0x00, 0x06, /* sequ_regs */ ++ 0x63, /* miscreg */ ++ 0x5f, 0x4f, 0x50, 0x82, 0x54, 0x80, 0xbf, 0x1f, ++ 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x9c, 0x8e, 0x8f, 0x28, 0x00, 0x96, 0xb9, 0xe3, ++ 0xff, /* crtc_regs */ ++ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, ++ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, ++ 0x01, 0x00, 0x0f, 0x00, /* actl_regs */ ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, 0xff, /* grdc_regs */ ++}, ++{ ++ /* index=0x0f no mode defined */ ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++}, ++{ ++ /* index=0x10 no mode defined */ ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++}, ++{ ++ /* index=0x11 vga mode 0x0f */ ++ 80, 24, 14, 0x00, 0x80, /* tw, th-1, ch, slength */ ++ 0x01, 0x0f, 0x00, 0x06, /* sequ_regs */ ++ 0xa3, /* miscreg */ ++ 0x5f, 0x4f, 0x50, 0x82, 0x54, 0x80, 0xbf, 0x1f, ++ 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x83, 0x85, 0x5d, 0x28, 0x0f, 0x63, 0xba, 0xe3, ++ 0xff, /* crtc_regs */ ++ 0x00, 0x08, 0x00, 0x00, 0x18, 0x18, 0x00, 0x00, ++ 0x00, 0x08, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, ++ 0x01, 0x00, 0x01, 0x00, /* actl_regs */ ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, 0xff, /* grdc_regs */ ++}, ++{ ++ /* index=0x12 vga mode 0x10 */ ++ 80, 24, 14, 0x00, 0x80, /* tw, th-1, ch, slength */ ++ 0x01, 0x0f, 0x00, 0x06, /* sequ_regs */ ++ 0xa3, /* miscreg */ ++ 0x5f, 0x4f, 0x50, 0x82, 0x54, 0x80, 0xbf, 0x1f, ++ 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x83, 0x85, 0x5d, 0x28, 0x0f, 0x63, 0xba, 0xe3, ++ 0xff, /* crtc_regs */ ++ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x14, 0x07, ++ 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, ++ 0x01, 0x00, 0x0f, 0x00, /* actl_regs */ ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, 0xff, /* grdc_regs */ ++}, ++{ ++ /* index=0x13 no mode defined */ ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++}, ++{ ++ /* index=0x14 no mode defined */ ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++}, ++{ ++ /* index=0x15 no mode defined */ ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++}, ++{ ++ /* index=0x16 no mode defined */ ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++}, ++{ ++ /* index=0x17 vga mode 0x01 */ ++ 40, 24, 16, 0x00, 0x08, /* tw, th-1, ch, slength */ ++ 0x08, 0x03, 0x00, 0x02, /* sequ_regs */ ++ 0x67, /* miscreg */ ++ 0x2d, 0x27, 0x28, 0x90, 0x2b, 0xa0, 0xbf, 0x1f, ++ 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, ++ 0x9c, 0x8e, 0x8f, 0x14, 0x1f, 0x96, 0xb9, 0xa3, ++ 0xff, /* crtc_regs */ ++ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x14, 0x07, ++ 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, ++ 0x0c, 0x00, 0x0f, 0x08, /* actl_regs */ ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x0e, 0x0f, 0xff, /* grdc_regs */ ++}, ++{ ++ /* index=0x18 vga mode 0x03 */ ++ 80, 24, 16, 0x00, 0x10, /* tw, th-1, ch, slength */ ++ 0x00, 0x03, 0x00, 0x02, /* sequ_regs */ ++ 0x67, /* miscreg */ ++ 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, ++ 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, ++ 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, ++ 0xff, /* crtc_regs */ ++ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x14, 0x07, ++ 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, ++ 0x0c, 0x00, 0x0f, 0x08, /* actl_regs */ ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x0e, 0x0f, 0xff, /* grdc_regs */ ++}, ++{ ++ /* index=0x19 vga mode 0x07 */ ++ 80, 24, 16, 0x00, 0x10, /* tw, th-1, ch, slength */ ++ 0x00, 0x03, 0x00, 0x02, /* sequ_regs */ ++ 0x66, /* miscreg */ ++ 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, ++ 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, ++ 0x9c, 0x8e, 0x8f, 0x28, 0x0f, 0x96, 0xb9, 0xa3, ++ 0xff, /* crtc_regs */ ++ 0x00, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, ++ 0x10, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, ++ 0x0e, 0x00, 0x0f, 0x08, /* actl_regs */ ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x0a, 0x0f, 0xff, /* grdc_regs */ ++}, ++{ ++ /* index=0x1a vga mode 0x11 */ ++ 80, 29, 16, 0x00, 0x00, /* tw, th-1, ch, slength */ ++ 0x01, 0x0f, 0x00, 0x06, /* sequ_regs */ ++ 0xe3, /* miscreg */ ++ 0x5f, 0x4f, 0x50, 0x82, 0x54, 0x80, 0x0b, 0x3e, ++ 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0xea, 0x8c, 0xdf, 0x28, 0x00, 0xe7, 0x04, 0xe3, ++ 0xff, /* crtc_regs */ ++ 0x00, 0x3f, 0x00, 0x3f, 0x00, 0x3f, 0x00, 0x3f, ++ 0x00, 0x3f, 0x00, 0x3f, 0x00, 0x3f, 0x00, 0x3f, ++ 0x01, 0x00, 0x0f, 0x00, /* actl_regs */ ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, 0xff, /* grdc_regs */ ++}, ++{ ++ /* index=0x1b vga mode 0x12 */ ++ 80, 29, 16, 0x00, 0x00, /* tw, th-1, ch, slength */ ++ 0x01, 0x0f, 0x00, 0x06, /* sequ_regs */ ++ 0xe3, /* miscreg */ ++ 0x5f, 0x4f, 0x50, 0x82, 0x54, 0x80, 0x0b, 0x3e, ++ 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0xea, 0x8c, 0xdf, 0x28, 0x00, 0xe7, 0x04, 0xe3, ++ 0xff, /* crtc_regs */ ++ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x14, 0x07, ++ 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, ++ 0x01, 0x00, 0x0f, 0x00, /* actl_regs */ ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, 0xff, /* grdc_regs */ ++}, ++{ ++ /* index=0x1c vga mode 0x13 */ ++ 40, 24, 8, 0x00, 0x00, /* tw, th-1, ch, slength */ ++ 0x01, 0x0f, 0x00, 0x0e, /* sequ_regs */ ++ 0x63, /* miscreg */ ++ 0x5f, 0x4f, 0x50, 0x82, 0x54, 0x80, 0xbf, 0x1f, ++ 0x00, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x9c, 0x8e, 0x8f, 0x28, 0x40, 0x96, 0xb9, 0xa3, ++ 0xff, /* crtc_regs */ ++ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, ++ 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, ++ 0x41, 0x00, 0x0f, 0x00, /* actl_regs */ ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0f, 0xff, /* grdc_regs */ ++}, ++{ ++ /* index=0x1d vga mode 0x6a */ ++ 100, 36, 16, 0x00, 0x00, /* tw, th-1, ch, slength */ ++ 0x01, 0x0f, 0x00, 0x06, /* sequ_regs */ ++ 0xe3, /* miscreg */ ++ 0x7f, 0x63, 0x63, 0x83, 0x6b, 0x1b, 0x72, 0xf0, ++ 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x59, 0x8d, 0x57, 0x32, 0x00, 0x57, 0x73, 0xe3, ++ 0xff, /* crtc_regs */ ++ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x14, 0x07, ++ 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, ++ 0x01, 0x00, 0x0f, 0x00, /* actl_regs */ ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, 0xff, /* grdc_regs */ ++}, ++}; ++ + /* Mono */ + static Bit8u palette0[63+1][3]= + { |