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| author | Frédéric Pétrot | 2022-01-06 22:01:06 +0100 |
|---|---|---|
| committer | Alistair Francis | 2022-01-08 06:46:10 +0100 |
| commit | 961738ffea964daad464389b3f06dd5b245fdf3c (patch) | |
| tree | b2b43bc5ddc29f2960c4538bbc407b84d563d5a8 /python/Pipfile | |
| parent | target/riscv: adding high part of some csrs (diff) | |
| download | qemu-961738ffea964daad464389b3f06dd5b245fdf3c.tar.gz qemu-961738ffea964daad464389b3f06dd5b245fdf3c.tar.xz qemu-961738ffea964daad464389b3f06dd5b245fdf3c.zip | |
target/riscv: helper functions to wrap calls to 128-bit csr insns
Given the side effects they have, the csr instructions are realized as
helpers. We extend this existing infrastructure for 128-bit sized csr.
We return 128-bit values using the same approach as for div/rem.
Theses helpers all call a unique function that is currently a fallback
on the 64-bit version.
The trans_csrxx functions supporting 128-bit are yet to be implemented.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220106210108.138226-17-frederic.petrot@univ-grenoble-alpes.fr
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'python/Pipfile')
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