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author | Fabiano Rosas | 2022-01-28 13:15:07 +0100 |
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committer | Cédric Le Goater | 2022-01-28 13:15:07 +0100 |
commit | f82db77761806613a62f622db9c1ca613ae1e6ed (patch) | |
tree | 218a079b24b1e6e6f19556470dcf1f83729f98ed /python/qemu/aqmp/events.py | |
parent | target/ppc: 74xx: System Reset interrupt cleanup (diff) | |
download | qemu-f82db77761806613a62f622db9c1ca613ae1e6ed.tar.gz qemu-f82db77761806613a62f622db9c1ca613ae1e6ed.tar.xz qemu-f82db77761806613a62f622db9c1ca613ae1e6ed.zip |
target/ppc: 74xx: Set SRRs directly in exception code
The 74xx does not have alternate/hypervisor Save and Restore
Registers, so we can set SRR0 and SRR1 directly.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220127201116.1154733-9-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Diffstat (limited to 'python/qemu/aqmp/events.py')
0 files changed, 0 insertions, 0 deletions