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| author | Vikram Garhwal | 2020-12-03 20:22:35 +0100 |
|---|---|---|
| committer | Peter Maydell | 2020-12-15 13:04:30 +0100 |
| commit | 8bbe61f3c10446603514aeee0aafebaaa00e8d07 (patch) | |
| tree | 729e26ebbd6112241bd458a991e99f1fe9f86ca1 /python/qemu/machine.py | |
| parent | usb: Add versal-usb2-ctrl-regs module (diff) | |
| download | qemu-8bbe61f3c10446603514aeee0aafebaaa00e8d07.tar.gz qemu-8bbe61f3c10446603514aeee0aafebaaa00e8d07.tar.xz qemu-8bbe61f3c10446603514aeee0aafebaaa00e8d07.zip | |
usb: Add DWC3 model
This patch adds skeleton model of dwc3 usb controller attached to
xhci-sysbus device. It defines global register space of DWC3 controller,
global registers control the AXI/AHB interfaces properties, external FIFO
support and event count support. All of which are unimplemented at
present,we are only supporting core reset and read of ID register.
Signed-off-by: Vikram Garhwal <fnu.vikram@xilinx.com>
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 1607023357-5096-3-git-send-email-sai.pavan.boddu@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'python/qemu/machine.py')
0 files changed, 0 insertions, 0 deletions