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| author | Frédéric Pétrot | 2022-01-06 22:01:08 +0100 |
|---|---|---|
| committer | Alistair Francis | 2022-01-08 06:46:10 +0100 |
| commit | 457c360f9c72f86ac6dd57f46a016dd361aaf3f7 (patch) | |
| tree | 72eb4ec3a856d803fb54bed65b045cc2c9a0a503 /python/tests/flake8.sh | |
| parent | target/riscv: modification of the trans_csrxx for 128-bit support (diff) | |
| download | qemu-457c360f9c72f86ac6dd57f46a016dd361aaf3f7.tar.gz qemu-457c360f9c72f86ac6dd57f46a016dd361aaf3f7.tar.xz qemu-457c360f9c72f86ac6dd57f46a016dd361aaf3f7.zip | |
target/riscv: actual functions to realize crs 128-bit insns
The csrs are accessed through function pointers: we add 128-bit read
operations in the table for three csrs (writes fallback to the
64-bit version as the upper 64-bit information is handled elsewhere):
- misa, as mxl is needed for proper operation,
- mstatus and sstatus, to return sd
In addition, we also add read and write accesses to the machine and
supervisor scratch registers.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220106210108.138226-19-frederic.petrot@univ-grenoble-alpes.fr
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'python/tests/flake8.sh')
0 files changed, 0 insertions, 0 deletions